VSC6511RC 查看數據表（PDF） - Vitesse Semiconductor

零件编号

产品描述 (功能)

生产厂家

VSC6511RC

Deserializer/Reclocker SMPTE 292M Serializer, Deserialzer, and

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC6511

SMPTE 292M Serializer, Deserialzer, and

Deserializer/Reclocker

CLK

DATA IN

Figure 3: Framer Signal Generation Timing Diagram

Timing Diagram #2: FRAMER Signal Generation

AV LINE 1

3FF 000 000 XYZ LN0 LN1 CR0 CR1

EAV SEQUENCE

HANC

3FF 000 000 XYZ

SAV SEQUENCE

AV LINE 2

3FF 000 000 XYZ LN0 LN1 CR0 CR1

EAV SEQUENCE

LINE

HANC

FRAME

D[19:0] Data Bus

As mentioned previously, in Serializer mode D[19:0] is configured as a input. In Deserializer and Deserial-

izer/Reclocker mode, D[19:0] is configured as an output.

The Data bus is TTL/CMOS logic level compatible. When configured as an input in the Serializer mode of

operation, it can also be 5V TTL-compatible by connecting Pin #1 [V53] to a 5V (+/-5%) supply rail.

The upper 10 bits of the data bus, D[19:10], are the data for the LUMINANCE or LUMA channel; Y[9:0].

D[19] is the MSB of the LUMA channel and D[10] is the LSB of the LUMA channel.

The lower 10 bits of the data bus, D[9:0], are the data for the CHROMINANCE or CHROMA channel;

C[9:0]. D[9] is the MSB of the CHROMA channel and D[0] is the LSB of the CHROMA channel.

Application Information

The VSC6511 cable driver output is intended to fully comply with the SMPTE 292M cable driver specifica-

tions. This includes an 800mV swing and a return loss of more than 15dB. The circuit shown in Figure 4 illus-

trates how to connect the output of the VSC6511 to the 75Ω cable and downstream device. The ISET resistor is

1.5kΩ.

Please refer to the latest VSC6511 Application Note or contact the factory for the most current information.

G52311-0, Rev 2.1

6/25/01

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Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

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