LTC1344A 查看數據表（PDF） - Linear Technology
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LTC1344A Datasheet PDF : 12 Pages
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LTC1344A
PIN FUNCTIONS
M0 (Pin 1): TTL Level Mode Select Input. The data on M0
is latched when LATCH is high.
VEE (Pin 2): Negative Supply Voltage Input. Can connect
directly to the LTC1543 VEE pin. Connect a 1µF capacitor
to ground.
R1C (Pin 3): Load 1 Center Tap.
R1B (Pin 4): Load 1 Node B.
R1A (Pin 5): Load 1 Node A.
R2A (Pin 6): Load 2 Node A.
R2B (Pin 7): Load 2 Node B.
R2C (Pin 8): Load 2 Center Tap.
R3A (Pin 9): Load 3 Node A.
R2B (Pin 10): Load 2 Node B.
R3C (Pin 11): Load 3 Center Tap.
GND (Pin 12): Ground Connection for Load 1 to Load 3.
GND (Pin 13): Ground Connection for Load 4 to Load 6.
VCC (Pin 14): Positive Supply Input. 4.75V ≤ VCC ≤ 5.25V.
R4B (Pin 15): Load 4 Node B.
R4A (Pin 16): Load 4 Node A.
R5B (Pin 17): Load 5 Node B.
R5A (Pin 18): Load 5 Node A.
R6A (Pin 19): Load 6 Node A.
R6B (Pin 20): Load 6 Node B.
LATCH (Pin 21): TTL Level Logic Signal Latch Input. When
LATCH is low the input buffers on M0, M1, M2 and DCE/
DTE are transparent. When LATCH is high the logic pins
are latched into their respective input buffers. The data
latch allows the select lines to be shared between multiple
I/O ports.
DCE/DTE (Pin 22): TTL Level Mode Select Input. DCE
mode is selected when high and DTE mode when low. The
data on DCE/DTE is latched when LATCH is high.
M2 (Pin 23): TTL Level Mode Select Input 1. The data on
M2 is latched when LATCH is high.
M1 (Pin 24): TTL Level Mode Select Input 2. The data on
M1 is latched when LATCH is high.
TEST CIRCUITS
C
A
R1
51.5Ω
S1
S2
Ω
ON
OFF
R2
51.5Ω
B
V ±7V OR ±2V
LTC1344A
R3
124Ω
1344 F01
Figure 1. Differential V.11 or V.35 Impedance Measurement
A, B
Ω
R1
51.5Ω
S1
S2
ON
ON
R2
51.5Ω
C
LTC1344A
R3
124Ω
V ±2V
1344 F02
Figure 2. V.35 Common Mode Impedance Measurement
4
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