TZA3004HL/C3 查看數據表（PDF） - Philips Electronics

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TZA3004HL/C3

SDH/SONET data and clock recovery unit STM1/4 OC3/12

Philips Electronics 

Philips Semiconductors

SDH/SONET data and clock recovery unit

STM1/4 OC3/12

Objective specification

TZA3004HL

FUNCTIONAL DESCRIPTION

The TZA3004HL recovers data and clock signals from an

incoming high speed bitstream. The input signal on DIN,

DINQ is buffered and amplified by the input circuitry.

The signal is then fed to the Alexander phase detector

where the phase of the incoming data is compared with

that of the internal clock. If the signals are out of phase, the

phase detector generates (UP or DOWN) correction

pulses that shift the phase of the VCRO (Voltage

Controlled Ring Oscillator) output in discrete amounts, ∆ϕ,

until the clock and data signals are in phase.

The technique used is based on principles first proposed

by J.D.H. Alexander, hence the phase detector’s name.

The eye pattern of the incoming data is sampled at three

instants A, T and B (see Fig.3). When clock and data

signals are synchronized (locked), A is in the centre of the

data bit, T is in the vicinity of the next transition, and B is in

the centre of the bit following the transition. If the same

level is recorded at both A and B, a transition has not

occurred and no action is taken regardless of the value

at T. If A and B are different, however, a transition has

occurred and the phase detector uses the value at T to

determine whether the clock was too early or too late with

respect to the data transition. If A and T are the same, but

different from B, the clock was too early and needs to be

slowed down a little. The Alexander phase detector then

generates a DOWN pulse which stretches a single output

pulse from the ring oscillator by approximately 0.25% (or

4 ps in STM4 mode; 4 ps is 0.25% of the 1.608 ns bit

period). This forces the VCRO to run at a slightly lower

frequency for one bit period. The phase of the clock is thus

shifted fractionally with respect to the data.

If, on the other hand, B and T are the same but different

from A, the clock was too late and needs to be speeded up

for synchronization. The phase detector generates an UP

pulse forcing the VCRO to run at a slightly higher

frequency (+0.25%) for one bit period. The phase of the

clock is shifted with respect to the data (as above, but in

the opposite direction). Only the proportional path is active

while these phase adjustments are being made. Because

the instantaneous frequency of the VCRO can be changed

only in one of two discrete steps (±0.25%), this type of loop

is also known as a Bang/Bang PLL.

If not only the phase but also the frequency of the VCRO

is incorrect, a long train of UP or DOWN pulses will be

generated. This pulse train is integrated to generate a

control voltage that is used to shift the centre frequency of

the VCRO. Once the correct frequency has been

established, the phase will need to be adjusted for

synchronization. The proportional path adjusts the phase

of the clock signal, while the integrating path adjusts the

centre frequency.

The frequency window detector checks that the VCRO

frequency is within a 1000 ppm (parts per million) window

around the required frequency. It compares the output of

frequency divider 2 with the reference frequency at CREF,

CREFQ (19.44 MHz or 38.88 MHz as available; see

Table 2). If the VCRO frequency is found to be outside this

window, the frequency window detector disables the

Alexander phase detector and forces the VCRO output to

a frequency within the window. The phase detector then

starts acquiring lock again. Because of the loose coupling

(1000 ppm), the reference frequency doesn’t need to be

highly accurate or stable. Any crystal based oscillator that

generates a reasonably accurate frequency (e.g. 100ppm)

)will do.

Since sampling point A is always in the centre of the eye

pattern when the data and clock signals are in phase

(locked), the values recorded at this point are taken as the

retrieved data. The data and clock signals are available at

the CML output buffers, which are capable of driving a

50 Ω load.

handbook, halfpaDgeATA

A

T

B

CLOCK

MGK143

Fig.3 Data sampling.

Power Control (PC)

The TZA3004HL contains an on-board voltage regulator.

An external power transistor is needed to deliver supply

current, IEE, to this circuit. The required external circuit is

straightforward, and can be built using a few components.

A suitable circuit is depicted in Fig.4. A different

configuration could be used, as long as the power supply

rejection ratio is greater than 60 dB for all frequencies.

The inductor is a (lossy) 1 µH RF-choke (EMI) with an

impedance greater than 50 Ω at frequencies higher than

2 MHz. Any transistor with a β > 100 and enough current

sink capability can be used.

The TZA3004HL can also be used with a -5V or -5.2V

supply voltage. The only adaption that has to be made to

the Power Control circuit is resistor R of 2Ω. This should

be 6.8Ω with a -5V supply and 8.2Ω with a -5.2V supply.

1998 Feb 09

6

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