TZA3004HL 查看數據表（PDF） - Philips Electronics

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TZA3004HL

SDH/SONET data and clock recovery unit STM1/4 OC3/12

Philips Electronics 

Philips Semiconductors

SDH/SONET data and clock recovery unit

STM1/4 OC3/12

Objective specification

TZA3004HL

POSITIVE SUPPLY APPLICATION

Due to the versatile design of the TZA3004HL, the device

can also operate in a positive supply application, although

some pins have a different mode of operation. This section

deals with these differences and supports the user with

successful application of the TZA3004HL in a +5V

environment. A sample application diagram can be found

in figure 4. Note that all GND pins are now connected to

VCC. All VEE pins are not connected to ground, but to pin

25, the regulated voltage from the power controller.

Loop mode and normal mode output select (ENL)

In a positive supply application, the default RF output will

be the LOOP MODE outputs. Due to the decoding logic at

the ENL pin, it is only possible to select the pins

DLOOP(Q) and CLOOP(Q) as outputs or enable all

outputs. If ENL is connected to VCC (+5V), the LOOP

MODE outputs are active. All outputs become active If

ENL is connected to pin VEE (the voltage on pin 25 is

approximately 3.3V below VCC). Beware not to connect

ENL to ground, this would destroy the IC. In the positive

supply application the NORMAL MODE outputs can not be

selected anymore.

Loss of signal detect and Lock detect (LOS & LOCK)

In the negative supply application, LOS and LOCK are

open collector outputs, that require pull-up resistors to a

positive supply. In the positive supply application, the

pull-up voltage would be higher then the positive supply

and the LOS and LOCK signals would not be TTL

compatible. The internal circuit at pins LOS and LOCK can

however be used in a current mirror configuration. It

requires only an external PNP transistor, BC857 or

equivalent, to mirror the current. A 10kΩ pull-down resistor

to ground yields a TTL compatible signal again, albeit

inverted. The table below shows the meaning of the LOS

and LOCK flag, when used according to the application

schematic of figure 4.

Table 3 LOS and LOCK indication for positive supply

SIGNAL

LOS active

LOS inactive

LOCK active

LOCK inactive

DESCRIPTION

Loss-of-signal; BER >5 10-2

No loss-of-signal; BER < 1 10-3

Reference clock present and VCO in 1000 ppm window

No reference clock present or VCO outside 1000 ppm window

LEVEL

0V (ground)

+5V (VCC)

0V (ground)

+5V (VCC)

TTL

LOW

HIGH

LOW

HIGH

Divider settings

The reference frequency dividers and the STM mode

selectors still operate the same in a positive supply

application. The only difference is that pins formerly

connected to GND (ground) should now be connected to

VCC (+5V), whereas pins connected to VEE still should be

connected to pin VEE (pin 25). Connection to ground (0V)

will damage the IC.

RF input/outputs

All RF inputs, outputs and internal signals of the

TZA3004HL are referenced to the most positive supply,

pins GND. In the positive supply application, this means all

RF signals are referenced to VCC. Therefore a clean VCC

rail is of ultimate importance for proper RF performance.

The best performance is obtained when the transmission

line reference plane is also decoupled to the VCC. Careful

design of VCC and good decoupling schemes should be

taken into account. While designing the printed circuit

board, bear in mind that the VCC has become what was

formerly ground.

1998 Feb 09

9

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