SY89426 查看數據表（PDF） - Micrel

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产品描述 (功能)

生产厂家

SY89426

SONET OC-12/OC-3 CLOCK SYNTHESIZER

Micrel 

Micrel, Inc.

Precision Edge®

SY89426

PACKAGE/ORDERING INFORMATION

GND

GND

SEL39

SEL78

RFCK

VCC

NC

25 24 23 22 21 20 19

26

18

27

17

28

PLCC

16

1

TOP VIEW

15

J28-1

2

14

3

13

4

12

5 6 7 8 9 10 11

VCC

VCC

CK622P

CK622N

VCCO

CK155

GND

28-Pin PLCC (J28-1)

Ordering Information(1)

Part Number

Package Operating

Type

Range

Package

Marking

Lead

Finish

SY89426JC

SY89426JCTR(2)

SY89426JY(3)

SY89426JYTR(2, 3)

J28-1

J28-1

J28-1

J28-1

Commercial

SY89426JC

Sn-Pb

Commercial

SY89426JC

Sn-Pb

Industrial

SY89426JY with

Matte-Sn

Pb-Free bar line indicator Pb-Free

Industrial

SY89426JY with

Matte-Sn

Pb-Free bar line indicator Pb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.

2. Tape and Reel.

3. Pb-Free package is recommended for new designs.

PIN DESCRIPTION

INPUTS

OUTPUTS

RFCK [Reference Clock] TTL

Reference clock IN. (38.88, 51.84 or 77.76MHz).

CK622P, CK622N [622 Clock Output] Differential PECL.

622.08MHz output clock from PLL B.

SEL39 [38.88MHz Select] TTL

CK155 [155 Clock Out] Single-ended PECL

Logic HIGH on this pin denotes a 38.88MHz input reference 155.52MHz output clock.

clock. Tie to logic LOW if input is not 38.88MHz.

SEL78 [77.76MHz Select] TTL

Logic HIGH on this pin denotes a 77.76MHz input reference

clock. Tie to logic LOW if input is not 77.76MHz.

RST [Reset] TTL

Tie to logic LOW for normal operation; logic HIGH forces reset

of internal Phase Detector & feedback dividers.

FLTRP, FLTRN [Loop Filter, Pos & Neg] Analog

Connect a series RC loop filter between these pins. The

suggested RC values are 500Ω and 0.1µF, as shown in the

Typical Application.

RETRFCK [Retimed Reference Clock Out] TTL

An output clock with the same frequency as the input Reference

Clock (RFCK) and a 45-55% duty cycle. This output is derived

by dividing the 622.08MHz output by the appropriate factor

(e.g., divide by 16 for a 38.88MHz inout reference; divide by

12 for 51.84Mhz in; or divide by 8 for 77.76MHz in).

POWER & GROUND

VCC

VCCO

GND

+5V for internal circuits.

+5V for PECL outputs.

Ground (0 volts).

DISC [Disable Clock] TTL

Logic HIGH on this pin disables the Retimed Reference Clock

output RETRFCK); if this output is not required, it is

recommended that it be disabled to reduce switching noise. A

logic LOW enables the output.

M9999-112105

hbwhelp@micrel.com or (408) 955-1690

2

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