VSC9142 查看數據表（PDF） - Vitesse Semiconductor

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VSC9142

STS-48c Packet/ATM Over SONET/SDH Device With Integrated Mux/Demux and Clock and Data Recovery

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC9142

STS-48c Packet/ATM Over SONET/SDH Device

With Integrated Mux/Demux and Clock and Data Recovery

Line Interface (PHY)

• A Loss of Optical Carrier (LOPC) input signal is provided for monitoring and alarm purposes.

• Selectable CMU Reference Clock for the transmit serial interface.

• Selectable CRU Reference Clock for the serial interface.

• CMU Lock Detect and Reference Detect indicators are available for the transmit serial interface.

• CRU Lock Detect and Reference Detect indicators are available for the receive serial interface.

• Internal and External Looptiming are avaliable between the CRU and the CMU.

• The CRU clock output can be selected to be the recovered clock from the incoming serial stream or from

an external clock. This feature can be used for looptiming applications under LOS conditions.

• The serial interface or the 4-bit parallel interface can be selected using the PHY4BITSEL pin. Only one

interface can be used at any time.

• Power-Down feature for the unused interface can be done by connecting the positive power supply pins of

the unused block to GND. Both serial and 4-bit parallel interfaces can be both independently powered

down.

• A parity bit, programmable for even/odd parity, is provided each for the incoming and outgoing parallel

datapaths.

• TLSYNC is provided for the parallel interface and is used for STS-192 applications.

• A reference clock output derived from the receive clock input can be programmed to be 8kHz, 19MHz,

38MHz, or 78MHz frequency locked to the receive clock.

• A reference clock output derived from the transmit clock input can be programmed to be 8kHz, 19MHz,

38MHz, or 78MHz frequency locked to the transmit clock.

Receive Section Overhead Processor (RSOP)

• Two mechanisms for frame alignment are provided. One is based on searching for A1/A2 framing pat-

terns and the other uses an external frame pulse (RLFP). The latter is intended for STS-192 applications.

• 12/24/48-bit A1/A2 framing patterns are supported.

• Out Of Frame (OOF) and Loss Of Frame (LOF) alarm condition are detected.

• The incoming data stream is optionally descrambled using the generating polynomial 1 + x6 + x7 with a

sequence length of 127.

• Section BIP-8 (B1) errors are detected and accumulated. Both individual and block mode accumulation

of B1 error indications are supported.

• The incoming data stream, before descrambling, is monitored for absence of transitions or “all-zero pat-

terns”. The Loss Of Signal (LOS) detection and termination criterias are programmable.

G52319-0, Rev. 3.1

6/12/00

 VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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