VITESSE
SEMICONDUCTOR CORPORATION
STS-48c Packet/ATM Over SONET/SDH Device
With Integrated Mux/Demux and Clock and Data Recovery
Preliminary Datasheet
VSC9142
• Packets stored in the Rx FIFO that are error marked
• Packet bytes stored in the Rx FIFO
• Number of received PPP padding bytes
• The SPE Transparent Mode is provided to allow all of the SPE payload to pass directly to the Rx FIFO
without further processing.
• A timestamp signal RXTS is provided to indicate when the first word of a packet is written into the Rx
FIFO.
Receive ATM Cell Processor (RACP)
• Cell Delineation is provided using shortened cyclic code with a generating polynomial 1 + x + x2 + x8.
The coset polynomial 1 + x2 + x4 + x8 can be added to the calculated HEC check bits before comparison.
• Single-bit header error correction is supported. The dropping of cells during single or multiple error
detection is programmable.
• The 48 byte information field is descrambled with a self-synchronizing descrambler polynomial 1 + x43.
Descrambling can be enabled/disabled.
• Cells can be filtered based on a programmable cell header pattern in the GFC, PTI, or CLP fields.
• The number of correctable and uncorrectable HEC errors detected, and the number of cells written to the
Rx FIFO are monitored.
• The Rx FIFO can accommodate storage of eight ATM cells.
Drop Side Interface (POS/ATM Interface)
• A parity bit, programmable for even/odd parity, is provided for each transmit and receive datapaths.
• The Drop Side Interface provides an industry compliant packet interface for POS operations.
• The packet interface supports word-level and packet-level transfer modes.
• The DTPA signal is provided to indicate the waterlevel of the Tx FIFO counted at word level and is pro-
grammable.
• It is possible to force reset/flush the contents in the Tx FIFO via the CPU interface.
• It is possible to force reset/flush the contents in the Rx FIFO via the CPU interface.
• The Drop Side Interface provides a Single-PHY UTOPIA-3 interface for ATM operations.
• Two formats of the ATM cells are supported: 52 byte cell or 56 byte cell containing the HEC.
• The UTOPIA-3 interface supports both word-level and cell-level flow control.
Transmit ATM Cell Processor (TACP)
• The ATM cells are mapped into the STS-48c SPE or equivalent SDH VC-16-16c. Programmable idle/
unassigned cells are inserted into the cell stream.
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VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52319-0, Rev. 3.1
6/12/00