TQ8105P 查看數據表（PDF） - TriQuint Semiconductor

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TQ8105P

SONET/SDH Transceivers

TriQuint Semiconductor 

TQ8105/TQ8106

PRELIMINARY DATA SHEET

Function Description

PLL

The TQ8105 & TQ8106 incorporate high-stability, low-

jitter Phase Locked Loops (PLLs) running at 2488.32

MHz. The PLLs use external surface mounted loop filters

consisting of an RC network as shown in the diagrams

that accompany the values shown in Table 2. Analog

design principles should be applied to the loop filter

portions of the circuit to ensure optimal jitter generation

performance. To reduce cross-coupling of clocks, both

CDR clocks and analog pins should be isolated from the

transmit PLL clock and analog pins. An analog ground

plane under the two capacitors and the resistor, along

with guards around the filter pins is excellent practice, as

is a well-filtered analog supply (AVDD) and a clean

analog ground (AGND). The loop filter values specified in

this preliminary data sheet may change.

Reference clock sourcing can be through a variety of

mechanisms. As shown in Table 3, the MMS pin

determines whether the device operates in Master

mode (where the PLL reference comes in on either a

TTL or PECL/ECL pin), or a Slave mode (where the PLL

reference is derived from the DEMUX high-speed line

clock input). If the external reference clock pins are

used, note that they are logical ORs and that the

unused pin should be tied to (a) GND for unused

REFCKT, or (b) REFCKEN should be tied to VPP for TTL

reference operation. The reference clock frequency can

be selected from any number of values, as indicated in

Table 3. Note that the PLL may be bypassed, allowing

use of an external clock reference.

Internal dividers determine the operating line rate, as

shown in Table 3. The device is capable of operating at

STM1/STS-3 or STM4/STS-12 rates. The transmit PLL

provides high performance and compliance with ITU/

Bellcore requirements found in the first-generation

TQ8101. The TQ8106 receiver's CDR can be disabled

for backwards pin-compatibility with the TQ8105. For

circuits not requiring the TQ8106's CDR, the CDR is

disabled by floating NCDREN (pin 100). Further, the CDR

section of the TQ8106 can be powered down by

disconnecting the CDRGND and CDRAVDD pins, thereby

reducing power consumption. If the TQ8106 CDR is not

used, the CDR filter pins may be left unconnected.

The transmit PLL also provides constant-rate 38.88 MHz

and 51.84 MHz TTL outputs which may be tristated. The

38.88 MHz & 51.84 MHz output may also be achieved by

using high-speed receiver timing in Clock Source Mode

011 (see Table 3).

Framer

The TQ8105 and TQ8106 provide a clean interface to

devices from PMC-Sierra and others. The Out-of-Frame

(OOF) input is a state (level)-initiated event, rather than

the edge-triggered event found on TriQuint’s first-

generation TQ8101 transceiver. When OOF is high, the

TQ8105/TQ8106 initiates a frame search for a serial bit

pattern of twelve A1s (three A1s in OC3 mode) followed

by three A2s. If a match occurs, the device realigns

byte boundaries and issues a logic high on the DXSYNC

pin during the third A2. In the absence of OOF, the

device will not realign byte boundaries, but will report

any bit-level matching of twelve A1s (three A1s in OC3

mode) followed by three A2s as a DXSYNC pulse.

Framer circuit power may be switched off by a TTL low on

the FRPWR pin, saving approximately 0.25W. No further

DXSYNC pulses will be issued, though bit alignment is

preserved in the demux. Note that the OOF and FRPWR

pins may be tied together, powering the framer only when

bit realignment is required (this is not recommended

practice, however, due to the inrush currents that may

result).

Loopbacks

As part of the TQ8105 and TQ8106 on-chip diagnostics,

four loopback modes are supported. These are selected

by the dedicated pins LBM0 and LBM1, as shown in

Table 3. The loopback modes are shown in Figure 5.

For additional information and latest specifications, see our website: www.triquint.com

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