WED9LC6416V2010BI 查看數據表（PDF） - White Electronic Designs => Micro Semi

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产品描述 (功能)

生产厂家

WED9LC6416V2010BI

128Kx32 SSRAM/4Mx32 SDRAM

White Electronic Designs => Micro Semi 

WED9LC6416V

Symbol

SSCLK

SSADS

SSOE

SSWE

SSCE

SDCLK

SDCE

SDRAS

SDCAS

SDWE

Type

Input

Input

Input

Input

Input

Input

A0-16,

SDA10

Input

DQ0-31

BWE0-3

Input

Output

Input

Vcc, Vss

VCCQ

Supply

Supply

OUTPUT FUNCTIONAL DESCRIPTIONS

Signal

Pulse

Pulse

Pulse

Pulse

Pulse

Pulse

Level

Level

Pulse

Polarity

Function

Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.

Active Low

When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define the operation

to be executed by the SSRAM.

Active Low SSCE disable or enable SSRAM device operation.

Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.

Active Low SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE0-3.

When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define the operation

Active Low to be executed by the SDRAM.

Address bus for SSRAM and SDRAM

A0 and A1 are the burst address inputs for the SSRAM

During a Bank Active command cycle, A0-11, SDA10 defines the row address (RA0-10) when sampled at the

rising clock edge.

—

During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the

rising clock edge. In addition to the row address, SDA10 is used to invoke Autoprecharge operation at the

end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and A12 and A13 define

the bank to be precharged. If SDA10 is low, autoprecharge is disabled.

During a Precharge command cycle, SDA10 is used in conjunction with A12 and A13 to control which bank(s)

to precharge. If SDA10 is high, all banks will be precharged regardless of the state of A12 and A13. If

SDA10 is low, then A12 and A13 are used to define which bank to precharge.

—

Data Input/Output are multiplexed on the same pins.

BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM. BWE0

is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31.

Power and ground for the input buffers and the core logic.

Data base power supply pins, 3.3V (2.5V future).

January 20001

3

White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com

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