LRS1331 查看數據表（PDF） - Sharp Electronics

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LRS1331

Stacked Chip 16M Flash Memory and 4M SRAM

Sharp Electronics 

Stacked Chip (16M Flash & 4M SRAM)

Table 1. Pin Descriptions

PIN

A0 to A16

F-A17 to F-A19

S-A17

F-CE

S-CE1, S-CE2

F-WE

S-WE

F-OE

S-OE

S-LB

S-UB

F-RP

F-WP

F-RY/BY

DQ0 to DQ15

F-VCC

S-VCC

F-VPP

F-GND

S-GND

NC

T1 to T5

DESCRIPTION

Address Inputs (Common)

Address Inputs (Flash)

Address Input (SRAM)

Chip Enable Input (Flash)

Chip Enable Inputs (SRAM)

Write Enable Input (Flash)

Write Enable Input (SRAM)

Output Enable Input (Flash)

Output Enable Input (SRAM)

SRAM Byte Enable Input (DQ0 to DQ7)

SRAM Byte Enable Input (DQ8 to DQ15)

Deep Power Down Input (Flash)

Block erase and Word Write: VIH

Read: VIH

Deep Power Down: VIL

Write Protect Input (Flash)

Two Boot Blocks Locked: VIL

Ready/Busy Output(Flash)

During an Erase or Write operation: VOL

Block Erase and Word Write Suspend: HIGH-Z

Deep Power Down: VOH

Data Input and Outputs (Common)

Power Supply (Flash)

Power Supply (SRAM)

Write, Erase Power Supply (Flash)

Block Erase and Word Write: F-VPP = VPPLK

All Blocks Locked: F-VPP < VPPLK

Ground (Flash)

Ground (SRAM)

No Connection

Test Pins (Should be Open)

LRS1331

TYPE

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Output

Input/Output

Power

Power

Power

Power

Power

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Data Sheet

3

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