STPCI01 查看數據表（PDF） - STMicroelectronics

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STPCI01

PC Compatible Embedded Microprocessor

STMicroelectronics 

STPC INDUSTRIAL

s X86 Processor core

s Fully static 32-bit 5-stage pipeline, x86

processor fully PC compatible.

s Access up to 4GB of external memory.

s 8Kbyte unified instruction and data cache

with write back capability.

s Parallel processing integral floating point unit,

with automatic power down.

s Clock core speeds up to 100 MHz.

s Fully static design for dynamic clock control.

s Low power and system management modes.

s Optimized design for 3.3V operation.

s DRAM Controller

s Integrated system memory and graphic frame

memory.

s Supports up to 128-MByte system memory in

4 banks and down to as little as 2Mbytes.

s Supports 4-MByte, 8-MByte, 16-MByte, and

32-MByte single-sided and double-sided

DRAM SIMMs.

s Four quad-word write buffers for CPU to

DRAM and PCI to DRAM cycles.

s Four quad-word read prefetch buffers for PCI

masters.

s Supports Fast Page Mode & EDO DRAMs.

s Programmable timing for DRAM parameters

including CAS pulse width, CAS pre-charge

time, and RAS to CAS delay.

s 60, 70, 80 & 100ns DRAM speeds.

s Memory hole between 1 MByte & 8 MByte

supported for PCI/ISA busses.

s Hidden refresh.

s Graphics Controller

s 64-bit windows accelerator.

s Complete backward compatibility to VGA and

SVGA standards.

s Hardware acceleration for text (generalized

bit map expansion), bitblts, transparent blts

and fills.

s Up to 64 x 64 bit graphics hardware cursor.

s Up to 4MB long linear frame buffer.

s 8, 16, 24 and 32 bit pixels.

s Drivers for Windows and other operating

systems.

s CRT Controller

s Integrated 135MHz triple RAMDAC allowing

for 1280 x 1024 x 75Hz display.

s Requires external frequency synthesizer and

reference sources.

s 8, 16, 24 and 32-bit pixels.

s Interlaced or non-interlaced output.

s TFT Interface

s Programmable panel size up to 1024 by 1024

pixels.

s Support for 640 x 480, 800 x 600 & 1024 x

768 active matrix TFT flat panels with 9, 12,

18-bit interface.

s Support 1 & 2 Pixels per Clock.

s Programmable image positionning.

s Programmable blank space insertion in text

mode.

s Programmable horizontal and vertical image

expansion in graphic mode.

s A fully programmable PWM (Pulse Width

Modulator) signals to adjust the flat panel

brightness and contrast.

s Supports PanelLinkTM high speed serial

transmitter externally for high resolution

panel interface.

s PCI Controller

s Fully compliant with PCI Version 2.1

specification.

s Integrated PCI arbitration interface. Up to 3

masters can connect directly. External PAL

allows for greater than 3 masters.

s Translation of PCI cycles to ISA bus.

s Translation of ISA master initiated cycle to

PCI.

s Support for burst read/write from PCI master.

s 0.33X and 0.5X CPU clock PCI clock.

s Local Bus interface

s 66MHz, low latency bus.

s Asynchronous / synchronous.

s 22-bit address and 16-bit data busses.

s 2 Programmable Flash EPROM Chip Select.

s 4 Programmable I/O Chip Select.

s Separate memory and I/O address spaces.

s Memory prefetch (improved performances).

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Issue 1.1

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