STPCI01 查看數據表（PDF） - STMicroelectronics

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STPCI01

PC Compatible Embedded Microprocessor

STMicroelectronics 

GENERAL DESCRIPTION

The need for system configuration jumpers is

eliminated by providing address mapping support

for PCMCIA 2.0 / JEIDA 4.1 PC-Card memory

together with address windowing support for I/O

space.

Selectable interrupt steering from PC-Card to

internal system bus is also provided.

The STPC Industrial implements a multi-function

parallel port. The standard PC/AT compatible

logical address assignments for LPT1, LPT2 and

LPT3 are supported.

The parallel port can be configured for any of the

following 3 modes and supports the IEEE

Standard 1284 parallel interface protocol

standards as follow:

-Compatibility Mode (Forward channel, standard)

-Nibble Mode (Reverse channel, PC compatible)

-Byte Mode (Reverse channel, PS/2 compatible)

The STPC Industrial BGA package has 388 balls,

but this is not sufficient for all the integrated

functions, therefore some features are sharing the

same balls and can not be used at the same time.

The STPC Industrial configuration is done by

‘strap options’. It is a set of pull-up or pull-down

resistors on the memory data bus, checked on

reset, which auto-configure the STPC Industrial.

We can distinguish three main blocks

independently configurables : The ISA / Local

Bus block, the Serial 1 / TFT block, and the PCI /

PC Card block.

From the first block, we can activate either the ISA

bus and some IPC additionnal features, or the

Local bus, the parallel port and the second serial

interface.

From the second block, we can activate either the

first serial port, or the TFT extension to get from 4

bit per colour to 6 bit per colour.

From the third block, we can activate either the

PCI bus, or the PC Card interface (CardBus/

PCMCIA/ZoomVideo).

The STPC Industrial core is compliant with the

Advanced Power Management (APM)

specification to provide a standard method by

which the BIOS can control the power used by

personal computers. The Power Management

Unit module (PMU) controls the power

consumption providing a comprehensive set of

features that control the power usage and

supports compliance with the United States

Environmental Protection Agency’s Energy Star

Computer Program. The PMU provides following

hardware structures to assist the software in

managing the power consumption by the system.

- System Activity Detection.

- 3 power-down timers detecting system inactivity:

- Doze timer (short durations).

- Stand-by timer (medium durations).

- Suspend timer (long durations).

- House-keeping activity detection.

- House-keeping timer to cope with short bursts of

house-keeping activity while dozing or in stand-by

state.

- Peripheral activity detection.

- Peripheral timer detecting peripheral inactivity

- SUSP# modulation to adjust the system

performance in various power down states of the

system including full power on state.

- Power control outputs to disable power from

different planes of the board.

Lack of system activity for progressively longer

periods of time is detected by the three power

down timers. These timers can generate SMI

interrupts to CPU so that the SMM software can

put the system in decreasing states of power

consumption. Alternatively, system activity in a

power down state can generate SMI interrupt to

allow the software to bring the system back up to

full power on state. The chip-set supports up to

three power down states described above, these

correspond to decreasing levels of power savings.

Power down puts the STPC Industrial into

suspend mode. The processor completes

execution of the current instruction, any pending

decoded instructions and associated bus cycles.

During the suspend mode, internal clocks are

stopped. Removing power down, the processor

resumes instruction fetching and begins execution

in the instruction stream at the point it had

stopped. Because of the static nature of the core,

no internal data is lost..

Issue 1.1

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