VSC9112SB 查看數據表（PDF） - Vitesse Semiconductor

零件编号

产品描述 (功能)

生产厂家

VSC9112SB

STS-48c Physical Layer Packet/ATM Over SONET/SDH Device

Vitesse Semiconductor 

Datasheet

VSC9112

VITESSE

SEMICONDUCTOR CORPORATION

STS-48c Physical Layer

Packet/ATM Over SONET/SDH Device

• The received section trace message is checked for persistency. A mismatch alarm is supported.

CPU Interface

• All configuration bits are both writeable and readable and can be accessed regardless of the device clock

source status, except for the reset state. Configuration bits include selection bits, interrupt masking bits,

and programmable counter/control values.

• Eight programmable General Purpose Input/Output (GPIO) ports are available for monitoring and con-

trolling external signals. All GPIOs support bistable interrupts when configured as input ports.

• Clock activity monitors are implemented for all input clocks.

Bit Error Rate Monitoring

• Bit error rate monitoring is based on the Line BIP (B2) error code and is capable of measuring BERs

down to 10-10 .

• There are four independent BER monitors with individual accumulation periods and alarm thresholds.

• A saturation threshold is implemented for each BER monitor to specify the maximum number of errors

that can be accumulated per frame.

• The BER Signal Degrade (BER-SD) alarm is based on BER monitors 1 and 2.

• The BER Signal Fail (BER-SF) alarm is based on BER monitors 3 and 4.

JTAG

• Standard IEEE 1149.1 compliant JTAG interface.

Loopback Modes

• Equipment loopback is supported by looping the output from the Transmit Section Overhead Processor

(TSOP), in the transmit direction, back to the input of the Receive Section Overhead Processor (RSOP),

in the receive direction.

• Facility loopback is supported by looping the data received on the receive Line Side Interface back to the

transmit Line Side Interface.

• Section loopback is supported by looping the output from the Recieve Section Overhead Processor

(RSOP) in the receive direction back to the input of the Transmit Section Overhead Processor (TSOP), in

the transmit direction.

• Line loopback is supported by looping the output from the Recieve Line Overhead Processor (RLOP) in

the receive direction back to the input of the Transmit Line Overhead Processor (TLOP), in the transmit

direction.

• Drop side loopback is supported by looping the output from the Tx FIFO to the input of the Rx FIFO.

This loopback is supported for both packet and ATM cell mode.

G52210-0, Rev. 4.3

3/30/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 9

Share Link: