TMXF281553BAL-2-DB 查看數據表（PDF） - Agere -> LSI Corporation

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TMXF281553BAL-2-DB

Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

Agere -> LSI Corporation 

TMXF28155 Super Mapper

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

Preliminary Data Sheet

May 2001

1 Features (continued)

s Supports UPSR applications via the dedicated ring

interface and an external tributary selector.

s Supports all valid T1/E1/J1 multiplexing structures

into STS-1 and STS-3/STM-1:

— STS-3/STS-1/SPE/VTG/VTx

— STM-1/AU-3/TUG-2/TU-1x/VC-1x

— STM-1/AU-4/TUG-3/TUG-2/TU-1x/VC-1x

s Allows grooming of VTs/TUs in granularity of TUG-2s

within the STS-3/STM-1 signal.

s Supports J2 trace identifier monitoring/insertion.

s Configurable VT/TU slot selection for DS1, E1, and

J1 insertion and drop.

s Automatic receive monitor functions include VT/TU

RDI-V, REI-V, BIP-2 errors, AIS-V, LOP-V.

s Complies with GR-253-CORE, GR-499, ITU-T

G.707, G.704, G.783, T1.105, JT-G707, ETS 300

417-1-1.

1.6 M13 Features

s Sources may be broadcast, looped back, or routed

to/from a test-pattern generator or monitor.

s Any DS1 or E1 channel may be routed through the

jitter attenuator.

s DS3 may be configured for the M13 to interconnect

with the SPE, or external I/O to interconnect with the

M13 or SPE.

1.8 Jitter Attenuation

s PLL-free receive operation using built-in digital jitter

attenuator (in VT/VC mode or M13 mode).

s Configurable to meet jitter and MTIE requirements.

1.9 PDH Interfaces

s One DS3, 7x DS2.

s x28/x21 framed or unframed DS1 or E1 interfaces.

s One additional dedicated protection channel for

DS2/DS1/E1.

s Configurable multiplexer/demultiplexer for 28 DS1

signals, 21 E1 signals, or 7 DS2 signals to/from a

DS3 signal.

s Operates in either M23 or C-bit parity mode.

s Provisionable time slot selection for DS1, E1, and

DS2 insertion or drop.

s Full alarm monitoring and generation (LOS, BPV,

EXZ, OOF, SEF, AIS, RAI, FEAC, P-bit and C-bit par-

ity errors, FEBE).

s HDLC transmitter with 128-byte data buffer and

HDLC receiver with 128-byte data FIFO for the C-bit

parity path maintenance data link.

s DS3, DS2, DS1, and E1 loopback and loopback

request generation.

s Complies with T1.102, T1.107, T1.231, T1.403,

T1.404, GR 499, G.747, and G.775.

1.7 DS3/DS2/DS1/E1 Cross Connect

s Highly configurable interconnect for up to 28 DS1 or

21 E1 signals to/from the framer, external pins, M13,

or VT mappers.

s Supports up to seven DS2 signals to/from the exter-

nal pins or M13.

1.10 T1/E1/J1 Framing Features (x28/x21)

s x28/x21 T1/E1/J1 channels.

s Line coding: B8ZS, HDB3, ZCS, AMI, and

CMI (JJ20-11).

s T1 framing modes: ESF, D4, SLC ®-96, T1 DM DDS,

and SF (Ft only).

s E1 framing: G.704 basic and CRC-4 multiframe con-

sistent with G.706.

s J1 framing modes: JESF (Japan).

s Supports T1 and E1 unframed and transparent trans-

mission format.

s T1 signaling modes: transparent;

register and system access for ESF 2-state, 4-state,

and 16-state; D4 2-state, 4-state, and 16-state;

SLC-96 2-state, 4-state, and 16-state; J-ESF han-

dling groups maintenance and signaling; VT 1.5

SPE 2, 4, 16 state.

s E1 signaling modes: transparent;

register and system access for entire TS16 multi-

frame structure as per ITU G.732.

s Signaling debounce and change of state interrupt.

s V5.2 Sa7 processing.

2

Agere Systems Inc.

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