TMXF281553BAL-2-DB 查看數據表（PDF） - Agere -> LSI Corporation

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TMXF281553BAL-2-DB

Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

Agere -> LSI Corporation 

TMXF28155 Super Mapper

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

Preliminary Data Sheet

May 2001

Interface Specifications

3 Pin Information

Table of Contents

Contents

Page

3 Pin Information ..................................................................................................................................................... 8

3.1 456-Pin PBGA Pin Diagram ........................................................................................................................... 9

3.2 Pin Assignments ............................................................................................................................................ 9

3.3 Pin Descriptions ........................................................................................................................................... 15

3.3.1 High-speed I/O Pin Descriptions ........................................................................................................ 15

3.3.2 Protection Switch I/O Pin Description ................................................................................................ 16

3.3.3 Telecom Bus (Low-speed I/O) Pin Description .................................................................................. 16

3.3.4 TOAC and POAC ............................................................................................................................... 19

3.3.5 Miscellaneous Signals ........................................................................................................................ 20

3.3.6 DS3 Port ............................................................................................................................................. 20

3.3.7 M13 Multiplexer/Demultiplexer Receive Section ................................................................................ 22

3.3.8 Low-Order Path Overhead Access Channel ...................................................................................... 23

3.3.9 Framer PLL ........................................................................................................................................ 27

3.3.10 Test Pins .......................................................................................................................................... 30

3.4 Outline Diagram ........................................................................................................................................... 32

3.4.1 456-Pin PBGA .................................................................................................................................... 32

List of Figures

Figure 2. Pin Diagram of 456-Pin PBGA (Bottom View)........................................................................................... 9

Figure 3. Protection Switch..................................................................................................................................... 16

Figure 4. DS1/E1 to DXC Block Diagram ............................................................................................................... 23

List of Tables

Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order ....................................................................... 9

Table 2. Pin Assignments for 456-Pin PBGA by Signal Name .............................................................................. 12

Table 3. High-speed I/O Pin Descriptions ............................................................................................................. 15

Table 4. Protection Switch I/O Pin Description ...................................................................................................... 16

Table 5. Telecom Bus (Low-speed I/O) Pin Description ........................................................................................ 17

Table 6. TOAC and POAC .................................................................................................................................... 19

Table 7. Miscellaneous Signals ............................................................................................................................. 20

Table 8. DS3 Port .................................................................................................................................................. 21

Table 9. DS3 Port, C-Bit, and Datalink Access ..................................................................................................... 22

Table 10. M13 Multiplexer/Demultiplexer Receive Section ................................................................................... 22

Table 11. Low-Order Path Overhead Access Channel ......................................................................................... 23

Table 12. Multifunction System Interface Transmit Path Direction ........................................................................ 24

Table 13. Framer PLL ............................................................................................................................................ 27

Table 14. Microprocessor Interfaces ..................................................................................................................... 28

Table 15. General Purpose Interface .................................................................................................................... 29

Table 16. Test Pins ................................................................................................................................................ 30

Table 17. CDR Power ............................................................................................................................................ 30

Table 18. LVDS Control Pins ................................................................................................................................. 30

8

Agere Systems Inc.

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