GM76C8128CL/CLL
Write Cycle (3) (CS2 Controlled) (Notes 4)
tWC
ADD
tAS
tWR
tWP
/WE
tCW2
CS2
/CS1
DOUT
tCW1
tWHZ
tCLZ
tDW
tDH
DIN
VALID DATA
Notes:
1. /WE is High for Read Cycle.
2. Assuming that /CS1 Low transition or CS2 High transition occurs coincident with or after /WE Low
transition. Outputs remain in a high impedance state.
3. Assuming that /CS1 High transition or CS2 Low transition occurs coincident with or prior to /WE High
transition. Outputs remain in a high impedance state.
4. Assuming that /OE is high for write cycle. Outputs are in a high impedance state during this period.
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