MSM54V25632A-XXAGBK4 查看數據表（PDF） - Oki Electric Industry

零件编号

产品描述 (功能)

生产厂家

MSM54V25632A-XXAGBK4

131,072-Word x 32-Bit x 2-Bank Synchronous Graphics RAM

Oki Electric Industry 

¡ Semiconductor

MSM54V25632A

Bank Active and Masked Write Disable Command (CS, RAS, DSF = "Low", CAS, WE =

"High")

The Bank Active command activates the bank selected by BA. The Bank Active command

corresponds to conventional DRAM's RAS falling operation. Row addresses "A0 - A8 and BA"

are strobed. After this command, the write command and block write command for that bank

works as the no write per bit operation.

Bank Active and Masked Write Enable Command (CS, RAS = "Low", CAS, WE, DSF =

"High")

The Bank Active command activates the bank selected by BA. The Bank Active command

corresponds to conventional DRAM's RAS falling operation. Row addresses "A0 - A8 and BA"

are strobed. After this command, the write command and block write command for that bank

works as the write per bit operation.

Write Command (CS, CAS, WE, DSF, A8 = "Low", RAS = "High")

The Write command is required to begin burst write operation. Then burst access initial bit

column address is strobed.

Write with Auto Precharge Command (CS, CAS, WE, DSF = "Low", RAS, A8 = "High")

The Write with Auto Precharge command is required to begin burst write operation with

automatic precharge after the burst write. Any command that interrupts this operation cannot

be issued.

Masked Block Write Command (CS, CAS, WE, A8 = "Low", RAS, DSF = "High")

The Masked Block Write command is required to begin block write operation with column

mask. The masked block write operation performs writing in the 8 memory cells selected by

column addresses "A3 - A7". In this operation, data in color register is written to memory cells

with the column mask functions. At the same time, this command can perform write per bit

operation. The block write operation is not bursted.

6/66

Share Link: