EVAL-AD7853CB 查看數據表（PDF） - Analog Devices
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EVAL-AD7853CB Datasheet PDF : 34 Pages
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AD7853/AD7853L
Parameter
A Version1
B Version1 Units
Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, VOH
4
2.4
Output Low Voltage, VOL
0.4
Floating-State Leakage Current ± 10
Floating-State Output Capacitance4 10
Output Coding
4
V min
2.4
V min
0.4
V max
± 10
µA max
10
pF max
Straight (Natural) Binary
Twos Complement
ISOURCE = 200 µA
AVDD = DVDD = 4.5 V to 5.5 V
AVDD = DVDD = 3.0 V to 3.6 V
ISINK = 0.8 mA
Unipolar Input Range
Bipolar Input Range
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
4.6 (18)
0.4 (1)
4.6 (18)
(10)
0.4 (1)
µs max
µs max
µs min
(L Versions Only, –40°C to +85°C, 1 MHz CLKIN)
(L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN)
(L Versions Only)
POWER REQUIREMENTS
AVDD, DVDD
IDD
Normal Mode5
Sleep Mode6
With External Clock On
+3.0/+5.5
6 (1.9)
5.5 (1.9)
10
400
With External Clock Off
5
200
Normal Mode Power Dissipation
Sleep Mode Power Dissipation
With External Clock On
With External Clock Off
33 (10.5)
20 (6.85)
55
36
27.5
18
+3.0/+5.5
6 (1.9)
5.5 (1.9)
10
400
5
200
33 (10.5)
20 (6.85)
55
36
27.5
18
V min/max
mA max
mA max
µA typ
µA typ
µA max
µA typ
mW max
mW max
µW typ
µW typ
µW max
µW max
AVDD = DVDD = 4.5 V to 5.5 V. Typically 4.5 mA (1.5);
AVDD = DVDD = 3.0 V to 3.6 V. Typically 4.0 mA (1.5 mA)
Full Power-Down. Power Management Bits in Control Register
Set as PMGT1 = 1, PMGT0 = 0
Partial Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 1
Typically 1 µA. Full-Power Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 0
Partial Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 1
VDD = 5.5 V: Typically 25 mW (8); SLEEP = VDD
VDD = 3.6 V: Typically 15 mW (5.4); SLEEP = VDD
VDD = 5.5 V; SLEEP = 0 V
VDD = 3.6 V; SLEEP = 0 V
VDD = 5.5 V: Typically 5.5 µW; SLEEP = 0 V
VDD = 3.6 V: Typically 3.6 µW; SLEEP = 0 V
SYSTEM CALIBRATION
Offset Calibration Span7
Gain Calibration Span7
+0.05 × VREF/–0.05 × VREF
+1.025 × VREF/–0.975 × VREF
V max/min Allowable Offset Voltage Span for Calibration
V max/min Allowable Full-Scale Voltage Span for Calibration
NOTES
1Temperature ranges as follows: A, B Versions, –40°C to +85°C. For L Versions, A and B Versions fCLKIN = 1 MHz over –40°C to +85°C temperature range,
B Version fCLKIN = 1.8 MHz over 0°C to +70°C temperature range.
2Specifications apply after calibration.
3SNR calculation includes distortion and noise components.
4Sample tested @ +25°C to ensure compliance.
5All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs. Analog inputs @ AGND.
6CLKIN @ DGND when external clock off. All digital inputs @ DGND except for CONVST, SLEEP, CAL, and SYNC @ DVDD. No load on the digital outputs.
Analog inputs @ AGND.
7The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7853/AD7853L can calibrate. Note also that these are voltage spans
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–) ± 0.05 × VREF,
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be VREF ± 0.025 × VREF).
This is explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
REV. B
–3–
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