EVAL-AD7853CB 查看數據表（PDF） - Analog Devices

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EVAL-AD7853CB

3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs

Analog Devices 

AD7853/AD7853L

TYPICAL TIMING DIAGRAMS

Figures 2 and 3 show typical read and write timing diagrams.

Figure 2 shows the reading and writing after conversion in In-

terface Modes 2 and 3. To attain the maximum sample rate of

100 kHz (AD7853L) or 200 kHz (AD7853) in Interface Modes

2 and 3, reading and writing must be performed during conver-

sion. Figure 3 shows the timing diagram for Interface Modes 4

and 5 with sample rate of 100 kHz (AD7853L) or 200 kHz

(AD7853). At least 400 ns acquisition time must be allowed

(the time from the falling edge of BUSY to the next rising edge

of CONVST) before the next conversion begins to ensure that

the part is settled to the 12-bit level. If the user does not want to

provide the CONVST signal, the conversion can be initiated in

software by writing to the control register.

1.6mA IOL

TO OUTPUT

PIN

CL

100pF

+2.1V

200␮A IOH

Figure 1. Load Circuit for Digital Output Timing

Specifications

POLARITY PIN LOGIC HIGH

t1

tCONVERT = 4.6␮s MAX, 10␮s FOR L VERSION

t1 = 100 ns MIN, t5 = 50/90 ns MAX 5V/3V, t7 = 40/60 ns MIN 5V/3V

CONVST (I/P)

t2

BUSY (O/P)

tCONVERT

SYNC (I/P)

SCLK (I/P)

DOUT (O/P)

t5

THREE-

STATE

t3

1

t6

DB15

t7

t8

t9

5

6

t10

t6

DB11

t11

16

t12

DB0

THREE-

STATE

DB15

DB11

DB0

Figure 2. AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)

POLARITY PIN LOGIC HIGH

t1

CONVST (I/P)

t2

BUSY (O/P)

tCONVERT = 4.6␮s MAX, 10␮s FOR L VERSION

t1 = 100 ns MIN, t5 = 50/90 ns MAX 5V/3V, t7 = 40/60 ns MIN 5V/3V

tCONVERT

SYNC (O/P)

SCLK (O/P)

t4

1

t5

t9

5

6

t11

16

t6

t10

t12

DOUT (O/P)

DIN (I/P)

THREE-

STATE

t7

t8

DB15

DB15

DB11

DB11

DB0

DB0

THREE-

STATE

Figure 3. AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)

REV. B

–5–

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