EVAL-AD7853CB 查看數據表（PDF） - Analog Devices

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EVAL-AD7853CB

3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs

Analog Devices 

AD7853/AD7853L

ABSOLUTE MAXIMUM RATINGS1

(TA = +25°C unless otherwise noted)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V

Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V

Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V

REFIN/REFOUT to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V

Input Current to Any Pin Except Supplies2 . . . . . . . . ± 10 mA

Operating Temperature Range

Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W

θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7°C/W

Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . +260°C

SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW

θJA Thermal Impedance . . . 75°C/W (SOIC) 115°C/W (SSOP)

θJC Thermal Impedance . . . . 25°C/W (SOIC) 35°C/W (SSOP)

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >3 kV

NOTES

1Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

2Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Model

Linearity

Error

(LSB)1

Power

Dissipation

(mW)

Package

Options2

AD7853AN

±1

20

AD7853BN

± 1/2

20

AD7853LAN3

±1

6.85

AD7853LBN3

±1

6.85

AD7853AR

±1

20

AD7853BR

± 1/2

20

AD7853LAR3

±1

6.85

AD7853LBR3

±1

6.85

AD7853ARS

±1

6.85

AD7853LARS3

±1

6.85

EVAL-AD7853CB4

EVAL-CONTROL BOARD5

N-24

N-24

N-24

N-24

R-24

R-24

R-24

R-24

RS-24

RS-24

NOTES

1Linearity error refers to the integral linearity error.

2N = Plastic DIP; R = SOIC; RS = SSOP.

3L signifies the low power version.

4This can be used as a stand-alone evaluation board or in conjunction with the

EVAL-CONTROL BOARD for evaluation/demonstration purposes.

5This board is a complete unit allowing a PC to control and communicate with

all Analog Devices, Inc. evaluation boards ending in the CB designators.

PIN CONFIGURATIONS

DIP, SOIC AND SSOP

CONVST 1

24 SYNC

BUSY 2

SLEEP 3

23 SCLK

22 CLKIN

REFIN/REFOUT 4

21 DIN

AVDD 5 AD7853/53L 20 DOUT

AGND 6

TOP VIEW

(Not to Scale)

19 DGND

CREF1 7

CREF2 8

18 DVDD

17 CAL

AIN(+) 9

16 SM2

AIN(–) 10

15 SM1

NC 11

14 POLARITY

AGND 12

13 AMODE

NC = NO CONNECT

–6–

REV. B

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