EVAL-AD7853CB 查看數據表（PDF） - Analog Devices

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EVAL-AD7853CB

3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs

Analog Devices 

Pin Mnemonic

1 CONVST

2 BUSY

3 SLEEP

4

REFIN/

REFOUT

5

AVDD

6, 12 AGND

7

CREF1

8

CREF2

9 AIN(+)

10 AIN(–)

11 NC

13 AMODE

14 POLARITY

15 SM1

16 SM2

17 CAL

18 DVDD

19 DGND

20 DOUT

21 DIN

22 CLKIN

23 SCLK

24 SYNC

REV. B

PIN FUNCTION DESCRIPTIONS

AD7853/AD7853L

Description

Convert Start. Logic Input. A low to high transition on this input puts the track/hold into its hold mode and

starts conversion. When this input is not used, it should be tied to DVDD.

Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL, and

remains high until conversion is completed. BUSY is also used to indicate when the AD7853/AD7853L has

completed its on-chip calibration sequence.

Sleep Input/Low Power Mode. A Logic 0 initiates a sleep and all circuitry is powered down including the

internal voltage reference provided there is no conversion or calibration being performed. Calibration data

is retained. A Logic 1 results in normal operation. See Power-Down section for more details.

Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this appears

at the pin. This pin can be overdriven by an external reference or can be taken as high as AVDD. When this

pin is tied to AVDD, or when an externally applied reference approaches AVDD, the CREF1 pin should also be

tied to AVDD.

Analog Positive Supply Voltage, +3.0 V to +5.5 V.

Analog Ground. Ground reference for track/hold, reference and DAC.

Reference Capacitor (0.1 µF multilayer ceramic). This external capacitor is used as a charge source for the

internal DAC. The capacitor should be tied between the pin and AGND.

Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip

reference. The capacitor should be tied between the pin and AGND.

Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above

AVDD at any time, and cannot go below AIN(–) when the unipolar input range is selected.

Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above

AVDD at any time.

No Connect Pin.

Analog Mode Pin. This pin allows two different analog input ranges to be selected. A Logic 0 selects range

0 to VREF (i.e., AIN(+) – AIN(–) = 0 to VREF). In this case AIN(+) cannot go below AIN(–) and

AIN(–) cannot go below AGND. A Logic 1 selects range –VREF/2 to +VREF/2 (i.e., AIN(+) – AIN(–) =

–VREF/2 to +VREF/2). In this case AIN(+) cannot go below AGND so that AIN(–) needs to be biased to

+VREF/2 to allow AIN(+) to go from 0 V to +VREF V.

Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will

reverse the active edge of the serial clock (SCLK). A Logic 1 means that the serial clock (SCLK) idles high

and a Logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and

Table IX for the SCLK active edges.

Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of opera-

tion as described in Table X.

Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of opera-

tion as described in Table X.

Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A Logic 0 on this pin resets

all calibration control logic and initiates a calibration on its rising edge. There is the option of connecting a

10 nF capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This input

overrides all other internal operations. If the autocalibration is not required, this pin should be tied to a

logic high.

Digital Supply Voltage, +3.0 V to +5.5 V.

Digital Ground. Ground reference point for digital circuitry.

Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.

Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act

as an input pin or as a I/O pin depending on the serial interface mode the part is in (see Table X).

Master Clock Signal for the device (4 MHz for AD7853, 1.8 MHz for AD7853L). Sets the conversion and

calibration times.

Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the

type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and

SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin.

This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync

in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table X).

–7–

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