NE56610 查看數據表（PDF） - Philips Electronics

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NE56610

System reset

Philips Electronics 

Philips Semiconductors

System reset

Product data

NE56610/11/12-XX

TIMING DIAGRAM

The Timing Diagram shown in Figure 17 depicts the operation of the

device. Letters indicate events on the TIME axis.

A: At start-up, event ‘A’, the VCC and VOUT (RESET) voltages begin

to rise. The reset voltage initially starts to rise but then abruptly

returns to a LOW voltage state. This is due to VCC reaching a level

(approximately 0.8 V) which activates the internal bias circuitry

asserting a RESET state at VOUT.

B: At event ‘B’, the fixed internal delay time (tDLH) is initiated. This

is caused and coincident to VCC rising to the threshold level of VSH.

At this level the device is in full operation. The output remains in a

low voltage state as VCC rises above VSH. This is normal.

C: At event ‘C’, VCC is above the undervoltage detection threshold

(VSL) and the fixed internal delay time (tDLH) has elapsed. At this

instant the device releases the hold on VOUT and VOUT (RESET)

goes to a high state.

In a microprocessor-based system these events remove the reset

from the microprocessor, allowing the microprocessor to be fully

functional.

D-E: At event ‘D’, VCC begins to ramp down and VOUT follows. VCC

continues to fall until the undervoltage threshold (VSL) is reached at

‘E’. This causes the device to generate a reset signal.

E-F: Between ‘E’ and ‘F’, VCC recovers and starts to rise.

F: At event ‘F’, VCC reaches the upper threshold (VSH). Once again,

the tDLH fixed internal delay time is initiated.

G: At event ‘G’, VCC is above the VSL undervoltage detection

voltage and the tDLH fixed internal delay time has elapsed. At this

point the device releases the hold on VOUT and VOUT goes to a

HIGH state.

H-K: At event ‘H’, VCC is normal, but a manual reset voltage (HIGH

voltage state) has been applied to the M/R pin. This forces the

output into a reset (LOW voltage state). Removal of the manual

reset voltage, at ‘J’, from the M/R pin initiates the fixed internal delay

time, and at ‘K’, the internal delay time has elapsed and VOUT goes

to a HIGH voltage state.

L: At event ‘L’, VCC sags to the VSL undervoltage threshold level

and the output goes into low voltage reset condition.

M: At event ‘M’, the VCC voltage has deteriorated to a level where

normal internal circuit bias is no longer able to maintain the device

and VOUT reset assertion is no longer be guaranteed. As a result,

VOUT may exhibit a slight rise to something less than 0.8 V. As VCC

decays even further, VOUT reset also decays to zero.

VSH

VSS = VSL

V

VCC

∆VS

V

VOUT

RESET

tDLH

V

M/R

0

A

VRES

B

C

tDLH

tDLH

DE F

G

HJ

K

Figure 17. Timing diagram.

L

TIME

M

SL01381

2003 Oct 31

9

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