TDA9103-USER 查看數據表（PDF） - STMicroelectronics

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TDA9103-USER

TDA9103 USER’S MANUAL DEMONSTRATION BOARD

STMicroelectronics 

TDA9103 USER’S MANUAL DEMONSTRATION BOARD

If these loops have too great area, they will send

disturbing spikes to other circuitry by mutual induc-

tance. For that reason the best place for transistors

Q1 and Q10 is : near to the horizontal scanning

transistor. This, of course, could not be imple-

mented on present board, which does not incorpo-

rate the scanning stage.

The driver stage supply voltage, present on C20,

must be well filtered, since a ripple at this point will

induce variations of the power transistor desatura-

tion time, which will cause jitter.

When the TDA9103 is controlled OFF, for instance

by X-ray protection, Q2 will remain conductive,

which causes high dissipation in R47. This may be

solved if AC coupling is used between pin 21 and

driver stage Q1-Q10. This was not implemented on

present board.

III.4 - DC/DC Converter Section

III.4.1 - Keeping the Information Clean

The converter section receives two informations

from other parts of the chassis :

- A determined fraction of the voltage to be regu-

lated, which it will manage to keep equal to its

internal reference (5V),

- The voltage on the sense resistor R61, which is

always lower than 1.2V.

The internal references for comparison are con-

nected to the local ground (pin 19) ; consequently,

any voltage difference in the ground track could

influence the regulated voltage and the peak cur-

rent in Q6. To avoid this :

- The foot of the divider, R79 + C47, must be

grounded near to the IC (pin 19) ; if this voltage

comes from a transformer,it is better to carry the

information to the IC with two dedicated tracks,

- The ground track between R61 and IC must carry

low-value or DC currents, as explained in the first

paragraph.

III.4.2 - Avoiding Disturbing Spikes

When Q6 switches from ON to OFF, the path of the

current changes abruptly from Q6-R61 to D3-C25,

and this may give rise to parasitic voltages, by

mutual inductance, in all surrounding circuits

(please refer to the comments about C4 in Vertical

section). This effect will be minimized if both paths

Q6-R61 and D3-C25 are very near to each other ;

in other terms, if the loop Q6-R61-C25-R3 has a

small area.

The driver stage for Q6 is similar to the one for Q2

and the high surge currents in its gate may cause

parasitic spikes in the same way.

III.5 - Pincushion (E/W) Section

All the comments relative to DAC control of the

horizontal DC inputs also apply to the E/W section.

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility

for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result

from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.

Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all

information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life

support devices or systems without express written approval of SGS-THOMSON Microelectronics.

© 1995 SGS-THOMSON Microelectronics - All Rights Reserved

Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips

I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to

the I2C Standard Specifications as defined by Philips.

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