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TDA9103-USER

TDA9103 USER’S MANUAL DEMONSTRATION BOARD

STMicroelectronics 

TDA9103 USER’S MANUAL DEMONSTRATION BOARD

This transformer is made with a EI core from TDK

(ref. PC30 EI22/19/6-Z) whose specifications are

given in annexe.

For a proper working, this stage is to be loaded by

the following circuit (Figure 1).

Figure 1

BYW98-100

BUH715

1Ω

47Ω

II.1.1.5 - Vertical Deflection Stage

This is the typical application of the TDA8172 used

with a symetrical power supply ±12V in order to

avoid using a high value electrolytic capacitor.

This stage is designed for driving a yoke with the

following characteristics :

- L ≈ 5mH

- R ≈ 8Ω

II.1.1.6 - B+ Converter

The B+ is generated by a boost step up converter

working in current mode.

The power MOS Q6 starts to conduct at the begin-

ning of the line sawtooth and it stops when the

voltage on R61 (image of drain current of the MOS)

becomes greater than the output voltage of the

error amplifier (inside the TDA9103). This voltage

is set by the regulation loop.

The board offers two possibilites for choosing the

regulation loop :

- Local regulation of B+ : SW2 in position 1.

- EHT regulation : SW2 in position 2 and feedback

input on J25.

This second mode will be choosen when the board

is connected on a multi-frequency monitor.

The main features of this converter are the follow-

ing :

- Frequency range 31kHz - 64kHz

- Output voltage 70V - 140V

- Input voltage

- Output power

45V ±X%

35W max.

You will find in annexe A the specifications of the

inductance T2 used in this converter.

II.1.1.7 - Other Functions

X ray protection TP2

A level higher than 1.6V (TTL level) in this point

inhibits all the outputs (Horizontal, Vertical, SMPS,

Blanking).

Blanking output TP6

This output is activated in case of Xray detection,

loss of line synchro, power failure (VCC, ...) or

activation of the ON/OFF switch.

ON/OFF switch

When the voltage on pin 2 is smaller than 1V, the

HOUT, VOUT and SMPS outputs are disabled and

the BLANK output TP6 is activated.

CS switch J17

Theses 4 outputs are sequentially switched on (low

level) if the input horizontal frequency goes through

the following thresholds : 34kHz, 41kHz, 51kHz,

61kHz.

These frequencies are given for a free running

frequency equal to 27kHz.

The CS switch outputs could be used to switch the

S correction capacitors if necessary.

Frame Blanking TP11

This output is in fact the flyback generator of the

vertical booster TDA8172. It could be used for

blanking the videosignal during the frame retrace.

II.1.1.8 - Operation with Composite Sync

When using these standards, the board is not

driven directly by the sync signals but by a circuit

(microproc or something else) who generates the

Hsync and Vsync signals. Unfortunately, the Hsync

signal present generally a jump of phase during the

Vsync time. This phase jump disturb the line PLL

and it can take a long time to recover the rightphase

at the end of the vertical sync.

So, we have to inhibit the line PLLduring the vertical

return time (and a little later).

This is done by the diode D4 and the time constant

R80-C48. When Vsync is at HIGH level, the voltage

on pin 35 is high and the line PLL is inhibited.

The consequence is that the board will not work

with standards having an inverted polarity vertical

synchro. In this case, D4 must be removed or

Vsync must be inverted in order to have a correct

working of the line PLL.

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