CMX860 查看數據表（PDF） - MX-COM Inc

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CMX860

Telephone Signaling Transceiver

MX-COM Inc  

Telephone Signaling Transceiver

17

CMX860 Advance Information

4.12.2 General Control Register: 16-bit write-only ($E0)

This register controls general features of the CMX860 such as the Powersave mode, the IRQ mask bits and the

Relay Drive output. It also allows the fixed compromise equalizers in the Tx and Rx signal paths to be disabled if

desired, and sets the internal clock dividers to use either a 11.0592 or a 12.288 MHz XTAL frequency. All bits of

this register are cleared to 0 by a General Reset command.

Bit: 15 14 13

12

11

10

9

8

7

6

543210

0

0

0

Xtal freq

Hook

IRQ Mask

Equ

Rlydrv

Pwr

Rst

Irqnen

IRQ Mask Bits

Reserved

Bit 15-13

Xtal Frequency

Bit 12

Reserved, set to 000

This bit should be set according to the Xtal frequency.

b12 = 1 11.0592MHz

b12 = 0 12.2880MHz

Hook Detect IRQ

Mask

Bit 11

Tx and Rx Fixed

Compromise

Equalizer

Bit 10

This bit affects the operation of the IRQ bit of the Status Register as described in section 4.12.8

This bit allows the Tx and Rx fixed compromise equalizer in the modem transmit and receive

filter blocks to be disabled

b10 = 1 Disable equalizer

b10 = 0 Enable equalizer (1200bps modem mode)

Relay Drive

Bit 9

This bit directly controls the RDRV output pin.

b9 = 1

b9 = 0

RDRV output pin pulled to DVSS

RDRV output pin pulled to DVDD

Power-up

Bit 8

This bit controls the internal power supply to most of the internal circuits, including the Xtal

oscillator and VBIAS supply. Note that the General Reset command clears this bit, putting the

device into Powersave mode.

When the device is switched from Powersave mode to normal operation by setting the Power-

up bit to 1, about 20ms should be allowed for the external circuits, Xtal oscillator, and VBIAS to

stabilize before starting to use the transmitter or receiver.

Changing the Power-up bit to 1 clears all bits of the Transmit Mode and Receive Mode

Registers and clears b15 and b13-0 of the Status Register.

b8 = 1

b8 = 0

Device powered up normally

Powersave mode (all circuits except Ring Detect, Hook Detect, RDRV and

C-BUS interface disabled)

Reset

Bit 7

Setting this bit to 1 resets the CMX860’s internal circuitry, clearing all bits of the Transmit and

Receive Mode Registers and b15 and b13-0 of the Status Register.

b7 = 1 Internal circuitry in a reset condition.

b7 = 0 Normal operation

IRQ EN

( IRQ Output

Enable)

Bit 6

IRQ Mask Bits

Bit 5-0

Setting this bit to 1 enables the IRQ output pin.

b6 = 1

b6 = 0

IRQ pin driven low (to DVSS) if the IRQ bit of the Status Register = 1

IRQ pin disabled (high impedance)

These bits affect the operation of the IRQ bit of the Status Register as described in

Section 4.12.8.

Table 4: General Control Register

¤2000 MX-COM, Inc.

www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054

Doc. # 20480222.001

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

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