SDA6000 查看數據表（PDF） - Micronas

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产品描述 (功能)

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SDA6000

Teletext Decoder with Embedded 16-bit Controller M2

Micronas 

SDA 6000 / SDA 6001

PRELIMINARY DATA SHEET

Version 3.00

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GPT1 Auxiliary Timer in Reload Mode. . . . . . . . . . . . . . . . . . . . . . 7 - 17

GPT1 Timer Reload Configuration for PWM Generation . . . . . . . . 7 - 18

Auxiliary Timer of Timer Block 1 in Capture Mode. . . . . . . . . . . . . 7 - 19

Structure of Timer Block 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 20

Block Diagram of Core Timer T6 in Timer Mode . . . . . . . . . . . . . . 7 - 22

Concatenation of Core Timer T6 and Auxiliary Timer T5. . . . . . . . 7 - 23

Timer Block 2 Register CAPREL in Capture Mode . . . . . . . . . . . . 7 - 24

Timer Block 2 Register CAPREL in Reload Mode . . . . . . . . . . . . . 7 - 25

Timer Block 2 Register CAPREL in Capture-And-Reload Mode . . 7 - 26

RTC Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 40

RTC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 41

Block Diagram of the ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 48

ASC Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 49

Asynchronous Mode of Serial Channel ASC0 . . . . . . . . . . . . . . . . 7 - 51

Asynchronous 8-Bit Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 52

Asynchronous 9-Bit Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 53

IrDA Frame Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 54

Fixed IrDA Pulse Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 56

RXD/TXD Data Path in Asynchronous Modes . . . . . . . . . . . . . . . . 7 - 57

Synchronous Mode of Serial Channel ASC0 . . . . . . . . . . . . . . . . . 7 - 58

ASC0 Synchronous Mode Waveforms . . . . . . . . . . . . . . . . . . . . . 7 - 60

ASC0 Baud Rate Generator Circuitry in Asynchronous Modes . . . 7 - 62

ASC0 Baud Rate Generator Circuitry in Synchronous Mode . . . . 7 - 64

ASC_P3 Asynchronous Mode Block Diagram . . . . . . . . . . . . . . . . 7 - 65

Two-Byte Serial Frames with ASCII ‘at’ . . . . . . . . . . . . . . . . . . . . . 7 - 66

Two-Byte Serial Frames with ASCII ‘AT’ . . . . . . . . . . . . . . . . . . . . 7 - 67

ASC0 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 73

SFRs and Port Pins Associated with the SSC0 . . . . . . . . . . . . . . . 7 - 84

Synchronous Serial Channel SSC0 Block Diagram. . . . . . . . . . . . 7 - 85

Serial Clock Phase and Polarity Options . . . . . . . . . . . . . . . . . . . . 7 - 87

SSC0 Full Duplex Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 88

SSC Half Duplex Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 91

SSC0 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 92

SSC0 Error Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 94

I2C Bus Line Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 102

Physical Bus Configuration Example . . . . . . . . . . . . . . . . . . . . . . 7 - 104

SFRs and Port Pins Associated with the A/D Converter . . . . . . . 7 - 121

Clock System in M2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 4

M2’s Display Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 5

Priority of Clamp Phase, Screen Background and Pixel Layer Area 9 - 15

50Hz/100Hz mode(ABAB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 18

100 Hz Mode (AABB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 19

100 Hz Mode (AAAA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 20

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