FX980L7 查看數據表（PDF） - CML Microsystems Plc
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FX980L7 Datasheet PDF : 86 Pages
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TETRA Baseband Processor
1.3 Signal List
FX980
L6 Package Package
44 PLCC
#
Pin No. Pin No.
Signal
Name
Type
15
MCLK
I/P
16
SClk
O/P
17
CmdDat
BI
18
CmdFS
I/P
19
CmdRdDat
O/P
20
CmdRdFS
O/P
11
RxDat
O/P
12
RxFS
O/P
23
N_IRQ
O/P
14
N_RESET
I/P
24
SCANSEL
I/P
25
ITXP
O/P
26
ITXN
O/P
30
QTXP
O/P
29
QTXN
O/P
42
IRXP
I/P
41
IRXN
I/P
38
QRXP
I/P
37
QRXN
I/P
43
AUXADC1
I/P
44
AUXADC2
I/P
1
AUXADC3
I/P
2
AUXADC4
I/P
Description
Master clock input (typically 9.216MHz)
Serial interface clock
Command serial interface Data
Command serial interface Frame
Command serial interface Read Data
Command serial interface Read Frame
Receive serial interface Data
Receive serial interface Strobe
Interrupt request
Chip Reset
Scan Select (normally tied low)
Transmit "I" channel, positive output
Transmit "I" channel, negative output
Transmit "Q" channel, positive output
Transmit "Q" channel, negative output
Receive "I" channel, positive input
Receive "I" channel, negative input
Receive "Q" channel, positive input
Receive "Q" channel, negative input
Auxiliary ADC channel 1
Auxiliary ADC channel 2
Auxiliary ADC channel 3
Auxiliary ADC channel 4
© 1997 Consumer Microcircuits Limited
4
D/980/3
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