FX980L7 查看數據表（PDF） - CML Microsystems Plc

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FX980L7

TETRA Baseband Processor

CML Microsystems Plc 

TETRA Baseband Processor

FX980

1.5.2

Tx Data Path

The features described below give a high degree of flexibility for the user to compensate in the

baseband processing for non-ideal performance in the IF, RF and RF linear amplifier sections.

1.5.2.1 Modulator

This takes the 2-bit symbols, performs a Gray code conversion and uses a recursive adder to

generate a 3-bit code representing the 8 possible phase states. A look up table provides the digitally

encoded I and Q values for each phase state. The modulator function can be by-passed if required; in

this case the 3-bit code representing the 8 possible phase states which are passed to the look up

table is provided directly via the serial interface.

1.5.2.2 Filters

Digital filtering is applied to the data from the modulator; the coefficients are set as default to give a

Root Raised Cosine response with roll-off factor of 0.35. These FIR filters operate at 8x the incoming

symbol rate and are configured, for each channel, as two filters in cascade: the first filter has 79 taps

and the second filter has 49 taps. The first filter is used to enhance stop-band rejection and act as a

sampling correction filter and the second filter provides the primary shaping. Coefficients for the filters

may also be downloaded to the device via the serial interface; this gives the opportunity, if required, to

fine tune the frequency response of a complete system so as to minimise the BER or to use the

device in other applications. The filters can also be by-passed if required.

1.5.2.3 Gain Multiplier

This circuitry allows independent external control of the digital amplitudes in the I and Q channels to

12 bits of resolution. Extra circuits allow a mode of operation which will enable linear ramping up to a

maximum value, stay at this value for a specified duration, then ramp back down to zero. The

maximum value for each channel, the duration at maximum, the ramping up rate and the ramping

down rate are all programmable via the serial interface.

1.5.2.4 Offset Adjust

Offset registers allow any offsets introduced in the analogue sections of the transmit path to be

corrected digitally via the serial interface. The offset adjust has a resolution of 1 LSB and a maximum

value of 0.25x full scale.

1.5.2.5 Sigma-Delta D-A Converters and Reconstruction Filters

The converters are designed to have low distortion and >80dB dynamic range. These 3rd order

converters operate at a frequency of 128x symbol rate so as to over-sample the data at their inputs a

further 16 times. The reconstruction filters are 5th order, switched capacitor, low pass filters designed

to work in conjunction with an external RC.

1.5.2.6 Phase Pre-distortion

A further feature allows the user to compensate for a non-orthogonal carrier phase in the external

quadrature modulator by adding a programmable fraction of up to 1/8 of the filtered I and Q channel

signals to each other immediately prior to the DAC input.

1.5.2.7 Ramping Output Amplitude

A facility is provided to allow linear ramping of the outputs. This is accomplished, if enabled, by

multiplying the gain multiplier words by the ramping control register (RCR) value. The RCR is a 12-bit

word, representing a value from 0 to 1, which is designed to increment by an amount (INC) until its

maximum value. This value is held until a number of symbol times from the start of transmission

(TRD) when RCR decrements by an amount (DEC) until zero. INC, DEC and TRD are all 12-bit words

input via the serial interface prior to the start of a transmission.

© 1997 Consumer Microcircuits Limited

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D/980/3

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