DDU8C-5200M 查看數據表（PDF） - Data Delay Devices
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DDU8C-5200M Datasheet PDF : 4 Pages
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5-TAP, HCMOS-INTERFACED
FIXED DELAY LINE
(SERIES DDU8C)
DDU8C
data
delay
3
®
devices, inc.
FEATURES
• Five equally spaced outputs
• Fits standard 8-pin DIP socket
• Low profile
• Auto-insertable
• Input & outputs fully CMOS interfaced & buffered
• 10 T2L fan-out capability
PACKAGES
IN 1
T2 2
T4 3
GND 4
8 VDD
7 T1
6 T3
5 T5
IN 1
N/C 2
N/C 3
T2 4
N/C 5
T4 6
GND 7
14 VDD
13 N/C
12 T1
11 N/C
10 T3
9 N/C
8 T5
DDU8C-xx DIP
DDU8C-xxA1 Gull-Wing
DDU8C-xxB1 J-Lead
DDU8C-xxM Military DIP
Military SMD
DDU8C-xxMD1
DDU8C-xxMD4
FUNCTIONAL DESCRIPTION
The DDU8C-series device is a 5-tap digitally buffered delay line. The
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an
amount determined by the device dash number (See Table). The total
delay of the line is measured from IN to T5. The nominal tap-to-tap delay
increment is given by one-fifth of the total delay.
PIN DESCRIPTIONS
IN
T1-T5
VDD
GND
Signal Input
Tap Outputs
+5 Volts
Ground
SERIES SPECIFICATIONS
• Minimum input pulse width: 40% of total delay
• Output rise time: 8ns typical
• Supply voltage: 5VDC ± 5%
• Supply current: ICCL = 40µa typical
ICCH = 10ma typical
• Operating temperature: 0° to 70° C
• Temp. coefficient of total delay: 300 PPM/°C
DASH NUMBER SPECIFICATIONS
Part
Number
DDU8C-5050
DDU8C-5060
DDU8C-5075
DDU8C-5100
DDU8C-5125
DDU8C-5150
DDU8C-5175
DDU8C-5200
DDU8C-5250
Total
Delay (ns)
50 ± 2.5
60 ± 3.0
75 ± 4.0
100 ± 5.0
125 ± 6.5
150 ± 7.5
175 ± 8.0
200 ± 10.0
250 ± 12.5
Delay Per
Tap (ns)
10.0 ± 3.0
12.0 ± 3.0
15.0 ± 3.0
20.0 ± 3.0
25.0 ± 3.0
30.0 ± 3.0
35.0 ± 4.0
40.0 ± 4.0
50.0 ± 5.0
NOTE: Any dash number between 5004 and 5250
not shown is also available.
20%
20%
20%
20%
20%
VDD IN
T1
T2
T3
T4
DDU8C Functional diagram
T5 GND
©1997 Data Delay Devices
Doc #97013
DATA DELAY DEVICES, INC.
1
1/28/97
3 Mt. Prospect Ave. Clifton, NJ 07013
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