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HC5513BIM 查看數據表(PDF) - Intersil

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HC5513BIM Datasheet PDF : 18 Pages
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HC5513
Figure 15 shows the relationship between the saturation
guard voltage, the loop current and the loop resistance. Notice
from Figure 15 that for a loop resistance <1.2k(RSG =
21.4k) the SLIC is operating in the constant current feed
region and for resistances >1.2kthe SLIC is operating in the
resistive feed region. Operation in the resistive feed region
allows long loop and off-hook transmission by keeping the tip
and ring voltages off the rails. Operation in this region is
transparent to the customer.
50
VBAT = -48V, RSG = 21.4k
40
30
CONSTANT CURRENT
FEED REGION
SATURATION GUARD
VOLTAGE, VTR = 38V
20
VBAT = -24V, RSG =
10 RESISTIVE FEED
REGION
0
0
10
20
30
LOOP CURRENT (mA)
SATURATION GUARD
VOLTAGE, VTR = 13V
RL 100k
RL 100k
4k
1.5k
2k
700
<1.2kRRSG = 21.4k
<400RRSG =
FIGURE 15. VTR vs IL AND RL
The Saturation Guard circuit (Figure 13) monitors the tip to
ring voltage via the transconductance amplifier A1. A1
generates a current that is proportional to the tip to ring
voltage difference. I1 is internally set to sink all of A1’s current
until the tip to ring voltage exceeds 12.5V. When the tip to ring
voltage exceeds 12.5V (with no RSG resistor) A1 supplies
more current than I1 can sink. When this happens A2
amplifies its input current by a factor of 12 and the current
through R1 becomes the difference between I2 and the output
current from A2. As the current from A2 increases, the voltage
across R1 decreases and the output voltage on RDC
decreases. This results in a corresponding decrease in the
loop current. The RSG pin provides the ability to increase the
saturation guard reference voltage beyond 12.5V. Equation 3
gives the relationship between the RSG resistor value and the
programmable saturation guard reference voltage:
VSGREF = 12.5 + 5----R----S--1--G-0----5-
(EQ. 3)
where:
VSGREF = Saturation Guard reference voltage.
RSG = Saturation Guard programming resistor.
When the Saturation guard reference voltage is exceeded,
the tip to ring voltage is calculated using Equation 4:
VTR = RL × -R----L---1--+-6---.(--6-R--6--D---+--C---5-1----+----1-R--0---D-5---C----R2----)-S---G--6---0---0--
where:
VTR = Voltage differential between tip and ring.
RL = Loop resistance.
(EQ. 4)
For on-hook transmission RL = , Equation 4 reduces to:
VTR = 16.66 + 5----R----S--1--G-0----5-
(EQ. 5)
The value of RSG should be calculated to allow maximum
loop length operation. This requires that the saturation guard
reference voltage be set as high as possible without clipping
the incoming or outgoing VF signal. A voltage margin of -4V
on tip and -4V on ring, for a total of -8V margin, is
recommended as a general guideline. The value of RSG is
calculated using Equation 6:
RSG=
-----------------------------------------------------------------5---------1---0----5----------------------------------------------------------------
( VBAT
VMARGIN)
×
1
+
(---R-----D----C-6---10----0+----R-R---L--D----C----2----)
16.66V
(EQ. 6)
where:
VBAT = Battery voltage.
VMARGIN = Recommended value of -8V to allow a maximum
overload level of 3.1VPEAK.
For on-hook transmission, RL = , Equation 6 reduces to:
RSG = --V----B----A----T------–-----V----M-5----A----R-1---G0----5I--N------–----1----6---.--6---6----V--
(EQ. 7)
SLIC in the Standby Mode
Overall system power is saved by configuring the SLIC in the
standby state when not in use. In the standby state the tip
and ring amplifiers are disabled and internal resistors are
connected between tip to ground and ring to VBAT. This
connection enables a loop current to flow when the phone
goes off-hook. The loop current detector then detects this
current and the SLIC is configured in the active mode for
voice transmission. The loop current in standby state is
calculated as follows:
IL R--V---L-B----+A----T1----8--–-0---0-3----V--
where:
IL = Loop current in the standby state.
RL = Loop resistance.
VBAT = Battery voltage.
(EQ. 8)
(AC) Transmission Path
SLIC in the Active Mode
Figure 16 shows a simplified AC transmission model. Circuit
analysis yields the following design equations:
VTR = VTX + IM 2RF
(EQ. 9)
V---Z--T--T-X-- + -VZ----RR----XX-- = 1----0I--M-0----0-
VTR = EG IM ZL
(EQ. 10)
(EQ. 11)
62

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