SCAN182373ASSC 查看數據表（PDF） - Fairchild Semiconductor

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SCAN182373ASSC

Transparent Latch with 25Ω Series Resistor Outputs

Fairchild Semiconductor 

Truth Tables

Inputs

ALE

†AOE1

X

H

H

L

H

L

L

L

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

AI (0–8)

X

L

H

X

AO (0–8)

Z

L

H

AO0

Functional Description

The SCAN182373A consists of two sets of nine D-type

latches with 3-STATE standard outputs. When the Latch

Enable (ALE or BLE) input is HIGH, data on the inputs

(AI(0–8) or BI(0–8)) enters the latches. In this condition the

latches are transparent, i.e., a latch output will change

state each time its input changes. When Latch Enable is

LOW, the latches store the information that was present on

Logic Diagram

BLE

Inputs

†BOE1

BI (0–8)

BO (0–8)

X

H

X

Z

H

L

L

L

H

L

H

H

L

L

X

BO0

AO0 = Previous AO before H-to-L transition of ALE

BO0 = Previous BO before H-to-L transition of BLE

† = Inactive-to-active transition must occur to enable outputs upon

power-up.

the inputs a set-up time preceding the HIGH-to-LOW tran-

sition of the Latch Enable. The 3-STATE standard outputs

are controlled by the Output Enable (AOE1 or BOE1) input.

When Output Enable is LOW, the standard outputs are in

the 2-state mode. When Output Enable is HIGH, the stan-

dard outputs are in the high impedance mode, but this

does not interfere with entering new data into the latches.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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