HEC4023BT 查看數據表（PDF） - Philips Electronics
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HEC4023BT Datasheet PDF : 3 Pages
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Philips Semiconductors
Triple 3-input NAND gate
Product specification
HEF4023B
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
In → On
HIGH to LOW
LOW to HIGH
Output transition times
HIGH to LOW
LOW to HIGH
5
10 tPHL
15
5
10 tPLH
15
5
10 tTHL
15
5
10 tTLH
15
65
135
ns
38 ns + (0,55 ns/pF) CL
25
50
ns
14 ns + (0,23 ns/pF) CL
15
30
ns
7 ns + (0,16 ns/pF) CL
65
130
ns
38 ns + (0,55 ns/pF) CL
30
60
ns
19 ns + (0,23 ns/pF) CL
25
45
ns
17 ns + (0,16 ns/pF) CL
60
120
ns
10 ns + (1,0 ns/pF) CL
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
60
120
ns
10 ns + (1,0 ns/pF) CL
30
60
ns
9 ns + (0,42 ns/pF) CL
20
40
ns
6 ns + (0,28 ns/pF) CL
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
1200 fi + ∑ (foCL) × VDD2
where
10
5500 fi + ∑ (foCL) × VDD2
fi = input freq. (MHz)
15
16 400 fi + ∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3
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