AD7890SQ-10 查看數據表（PDF） - Analog Devices
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AD7890SQ-10 Datasheet PDF : 29 Pages
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AD7890
Table 4. Ideal Input/Output Code Table for the AD7890-10
this is followed by the high input impedance stage of the track/
Analog Input1
Digital Output Code Transition
hold amplifier. The analog input range is, therefore, 0 V to 2.5 V
+FSR/2 − 1 LSB2 (9.995117 V) 011 . . . 110 to 011 . . . 111
into a high impedance stage with an input current of less than
+FSR/2 − 2 LSBs (9.990234 V) 011 . . . 101 to 011 . . . 110
50 nA. The designed code transitions occur on successive
+FSR/2 − 3 LSBs (9.985352 V) 011 . . . 100 to 011 . . . 101
integer LSB values (such as: l LSB, 2 LSBs, 3 LSBs . . . FS-1
AGND + 1 LSB (0.004883 V) 000 . . . 000 to 000 . . . 001
LSBs). Output coding is straight (natural) binary with 1 LSB =
AGND (0.000000 V)
AGND − 1 LSB (−0.004883 V)
111 . . . 111 to 000 . . . 000
111 . . . 110 to 111 . . . 111
FSR/4096 = 2.5 V/4096 = 0.61 mV. The ideal input/output
transfer function is shown in Table 6.
−FSR/2 + 3 LSBs (−9.985352 V) 100 . . . 010 to 100 . . . 011
−FSR/2 + 2 LSBs (−9.990234 V) 100 . . . 001 to 100 . . . 010
−FSR/2 + 1 LSB (−9.995117 V) 100 . . . 000 to 100 . . . 001
Table 6. Ideal Input/Output Code Table for the AD7890-2
Analog Input1
Digital Output Code Transition
+FSR − 1 LSB2 (2.499390 V) 111 . . . 110 to 111 . . . 111
1FSR is full-scale range and is 20 V with REF IN = 2.5 V.
21 LSB = FSR/4096 = 4.883 mV with REF IN = 2.5 V.
+FSR − 2 LSBs (2.498779 V)
+FSR − 3 LSBs (2.498169 V)
111 . . . 101 to 111 . . . 110
111 . . . 100 to 111 . . . 101
AD7890-4 Analog Input
AGND + 3 LSBs (0.001831 V) 000 . . . 010 to 010 . . . 011
Figure 5 shows the analog input section for the AD7890-4. The
analog input range for each of the analog inputs is 0 to 4.096 V
AGND + 2 LSBs (0.001221 V) 000 . . . 001 to 001 . . . 010
AGND + 1 LSB (0.000610 V) 000 . . . 000 to 000 . . . 001
into an input resistance of typically 15 kΩ. This input is benign
with no dynamic charging currents with the resistor attenuator
1FSR is full-scale range and is 2.5 V with REF IN = 2.5 V.
21 LSB = FSR/4096 = 0.61 mV with REF IN = 2.5 V.
stage followed by the multiplexer and in cases where MUX OUT is
connected to SHA IN this is followed by the high input
TRACK/HOLD AMPLIFIER
impedance stage of the track/hold amplifier. The designed code
transitions occur on successive integer LSB values (such as:
1 LSB, 2 LSBs, 3 LSBs . . . ). Output coding is straight (natural)
binary with 1 LSB = FSR/4096 = 4.096 V/4096 = 1 mV. The
ideal input/output transfer function is shown in Table 5.
The SHA IN input on the AD7890 connects directly to the input
stage of the track/hold amplifier. This is a high impedance input
with input leakage currents of less than 50 nA. Connecting the
MUX OUT pin directly to the SHA IN pin connects the
multiplexer output directly to the track/hold amplifier. The input
MUX OUT
voltage range for this input is 0 V to 2.5 V. If external circuitry is
REF OUT/
REF IN
2.5V
REFERENCE
2kΩ
TO ADC
REFERENCE
CIRCUITRY
connected between MUX OUT and SHA IN, then the user must
ensure that the input voltage range to the SHA IN input is 0 V to
2.5 V to ensure that the full dynamic range of the converter is
utilized.
The track/hold amplifier on the AD7890 allows the ADC to
accurately convert an input sine wave of full-scale amplitude to
VINX
6kΩ
9.38kΩ
200Ω1
12-bit accuracy. The input bandwidth of the track/hold is
greater than the Nyquist rate of the ADC even when the ADC is
AGND
AD7890-4
operated at its maximum throughput rate of 117 kHz (for example,
1EQUIVALENT ON-RESISTANCE OF MULTIPLEXER
Figure 5. AD7890-4 Analog Input Structure
Table 5. Ideal Input/Output Code Table for the AD7890-4
Analog Input1
Digital Output Code Transition
+FSR − 1 LSB2 (4.095 V)
111 . . . 110 to 111 . . . 111
+FSR − 2 LSBs (4.094 V) 111 . . . 101 to 111 . . . 110
+FSR − 3 LSBs (4.093 V) 111 . . . 100 to 111 . . . 101
AGND + 3 LSBs (0.003 V) 000 . . . 010 to 000 . . . 011
AGND + 2 LSBs (0.002 V) 000 . . . 001 to 000 . . . 010
AGND + 1 LSB (0.001 V) 000 . . . 000 to 000 . . . 001
the track/hold can handle input frequencies in excess of 58 kHz).
The track/hold amplifier acquires an input signal to 12-bit
accuracy in less than 2 μs. The operation of the track/hold is
essentially transparent to the user. The track/hold amplifier
goes from its tracking mode to its hold mode at the start of
conversion. The start of conversion is the rising edge of
CONVST (assuming the internal pulse has timed out) for
hardware conversion starts and for software conversion starts is
the point where the internal pulse is timed out. The aperture
time for the track/hold (for example, the delay time between the
external CONVST signal and the track/hold actually going into
1FSR is full-scale range and is 4.096 V with REF IN = 2.5 V.
21 LSB = FSR/4096 = 1 mV with REF IN = 2.5 V.
hold) is typically 15 ns. For software conversion starts, the time
depends on the internal pulse widths. Therefore, for software
AD7890-2 Analog Input
conversion starts, the sampling instant is not very well defined.
For sampling systems which require well defined, equidistant
The analog input section for the AD7890-2 contains no biasing
sampling, it may not be possible to achieve optimum performance
resistors and the selected analog input connects to the multi-
from the part using the software conversion start. At the end of
plexer and, in cases where MUX OUT is connected to SHA IN,
Rev. C | Page 12 of 28
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