AD7890SQ-10 查看數據表（PDF） - Analog Devices

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AD7890SQ-10

LC2MOS 8-Channel, 12-Bit Serial Data Acquisition System

Analog Devices 

AD7890

When using the device in the external-clocking mode, the

output register can be read at any time and the most up-to-date

conversion result is obtained. However, reading data from the

output register or writing data to the control register during

conversion or during the 500 ns prior to the next CONVST

results in reduced performance from the part. A read operation

to the output register has the most effect on performance with

the signal-to-noise ratio likely to degrade, especially when

higher serial clock rates are used while the code flicker from the

part also increases (see the Performance section).

Figure 7 shows the timing and control sequence required to

obtain optimum performance from the part in the external

clocking mode. In the sequence shown, conversion is initiated

on the rising edge of CONVST and new data is available in the

output register of the AD7890 5.9 μs later. Once the read

operation has taken place, a further 500 ns should be allowed

before the next rising edge of CONVST to optimize the settling

of the track/hold before the next conversion is initiated.

The diagram shows the read operation and the write operation

taking place in parallel. On the sixth falling edge of SCLK in the

write sequence the internal pulse is initiated. Assuming MUX OUT

is connected to SHA IN, 2 μs are required between this sixth

falling edge of SCLK and the rising edge of CONVST to allow

for the full acquisition time of the track/hold amplifier. With

the serial clock rate at its maximum of 10 MHz, the achievable

throughput rate for the part is 5.9 μs (conversion time) plus 0.6

μs (six serial clock pulses before internal pulse is initiated) plus

2 μs (acquisition time). This results in a minimum throughput

time of 8.5 μs (equivalent to a throughput rate of 117 kHz). If

the part is operated with a slower serial clock, it affects the

achievable throughput rate for optimum performance.

CONVST

SCLK

RFS

TFS

tCONVERT

500ns MIN

CONVERSION IS

INITIATED AND

TRACK/HOLD GOES

INTO HOLD

CONVERSION

ENDS 5.9µs

LATER

SERIAL READ

AND WRITE

OPERATIONS

READ AND WRITE

OPERATIONS SHOULD END

500ns PRIOR TO NEXT

RISING EDGE OF CONVST

Figure 7. External Clocking (Slave) Mode Timing Sequence for Optimum Performance

NEXT CONVERSION

START COMMAND

Rev. C | Page 14 of 28

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