ST16C650A(2005) 查看數據表（PDF） - Exar Corporation
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| ST16C650A Datasheet PDF : 0 Pages | |||
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REV. 5.0.1
ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
NAME
44- 48-
PLCC TQFP
PIN # PIN #
TYPE
DESCRIPTION
LPT2#
26
22
O Line Printer Port-2 Decode Logic Output (active low)
This pin functions as the PC standard LPT-2 printer port address decode logic out-
put, see Table 1.
MODEM OR SERIAL I/O INTERFACE
TX
13
8
O Transmit Data or wireless infrared transmit data
This output is active low in normal standard serial interface operation (RS-232,
RS-422 or RS-485) and active high in the infrared mode.
RX
11
7
I Receive Data or wireless infrared receive data
Normal received data input idles at logic 1 condition and logic 0 in the infrared
mode. The wireless infrared pulses are applied to the decoder. This input must be
connected to its idle logic state in either normal, logic 1, or infrared mode, logic 0,
else the receiver may report “receive break” and/or “error” condition(s).
RTS#
36
32
O Request to Send or general purpose output (active low)
This port may be used for one of two functions:
1) automatic hardware flow control, see EFR bit-6, MCR bit-1and IER bit-6.
2) RS485 half-duplex direction control, see XFR bits 2 and 5.
RTS# output must be asserted before auto RTS flow control can start.
CTS#
40
38
I Clear to Send or general purpose input (active low)
If used for automatic hardware flow control, data transmission will be stopped
when this pin is de-asserted and will resume when this pin is asserted again. See
EFR bit-7 and IER bit-7.
DTR#
37
33
O Data Terminal Ready or general purpose output (active low)
DSR#
41
39
I Data Set Ready input or general purpose input (active low)
CD#
42
40
I Carrier Detect input or general purpose input (active low)
RI#
43
41
I Ring Indicator input or general purpose input (active low)
ANCILLARY SIGNALS
XTAL1
18
14
I Crystal or external clock input. Caution: this input is not 5V tolerant.
XTAL2
19
15
O Crystal or buffered clock output
RCLK
10
5
I Receiver Clock
This input is used as external 16X clock input to the receiver section. Connect the
BAUDOUT# pin to this input externally.
BAUDOUT# 17
12
O Baud Rate Generator Output (active low)
This pin provides the 16X clock of the selected data rate from the baud rate gener-
ator. The RCLK pin must be connected externally to BAUDOUT# when the
receiver is operating at the same data rate.
When the PC mode is selected, the baud rate generator clock output is internally
connected to the RCLK input. This pin then functions as the LPT-1 printer port
decode logic output, see Table 3.
SEL
34
36
I PC Mode Select (active low)
When this input is at logic 0, it enables the on-board chip select decode function
according to PC ISA bus COM[4:1] and IRQ[4:3] port definitions. See Table 3 for
details. This pin has an internal 100kΩ pull-up resistor.
5
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