ST16C650A(2005) 查看數據表（PDF） - Exar Corporation
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| ST16C650A Datasheet PDF : 0 Pages | |||
ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
xr
REV. 5.0.1
2.0 FUNCTIONAL DESCRIPTIONS
2.1 Host Data Bus Interface
The host interface is 8 data bits wide with 3 address lines and control signals to execute bus read and write
transactions. The 650A supports 2 type of host interfaces: Intel and PC mode. The Intel bus interface is
selected by connecting SEL to a logic 1. The Intel bus interconnections are shown in Figure 3. The special PC
mode is selected when SEL is connected to a logic 0. The PC mode interconnections are shown in Figure 4.
FIGURE 3. ST16C650A INTEL BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR*
IOW*
CS#
INT
RESET
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
CS2#
INT
BAUDOUT#
RCLK
VCC
CS0
CS1
SEL
TX
RX
DTR#
RTS#
CTS#
DSR#
CD#
RI#
RESET
OP1#
OP2#
IOW
IOR
AS#
GND
VCC
FIGURE 4. ST16C650A PC MODE INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A14
A15
AEN#
IOR#
IOW#
IRQn
IRQ4
IRQ3
RESET
VCC
GND
GND
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AEN*
IOR#
IOW#
IRQA
IRQB
IRQC
S3
S2
S1
RESET
VCC
CS0
CS1
TX
RX
DTR#
RTS#
CTS#
DSR#
CD#
RI#
OP1#
SEL
IOW
IOR
AS#
GND
VCC
8
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