AD698 查看數據表（PDF） - Analog Devices
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AD698 Datasheet PDF : 12 Pages
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AD698
Note that VOS should be chosen so that R3 cannot have negative
value .
Figure 12 shows the desired response.
VOUT (VOLTS)
+10
–0.1 +5
+0.1d (INCHES)
Figure 12. VOUT (0 V–10 V Full Scale) vs. Displacement
(±0.1 Inch)
DESIGN PROCEDURE
SINGLE SUPPLY OPERATION
Figure 13 shows the single supply connection method.
+30V
Vps 6.8µF
0.1µF R5
C5
R6
1 –VS
AD698
+VS 24
R4
2 EXC1 OFFSET1 23
R3
3 EXC2 OFFSET2 22
SIGNAL
REFERENCE
4 LEV1
SIG REF 21
R1
5 LEV2
SIG OUT 20
R2
RL
VOUT
6 FREQ1 FEEDBACK 19
C1
C4 1000pF
7 FREQ2 OUT FILT 18
8 BFILT1
AFILT1 17
C2
C3
9 BFILT2
AFILT2 16
10 –BIN
–ACOMP 15
11 +BIN
12 –AIN
+ACOMP 14
+AIN 13
1M
A
B
PHASE
LAG/LEAD
NETWORK
C
D
PHASE LAG
A
B
C
RS
RT
RS
C
D
PHASE LEAD
A
B
RT
RS
C
C
C
D
PHASE LAG = Arc Tan (Hz RC);
PHASE LEAD = Arc Tan 1/(Hz RC)
WHERE R = RS// (RS + RT)
Figure 13. Interconnection Diagram for Single Supply
Operation
For single supply operation, repeat Steps 1 through 10 of the
design procedure for dual supply operation. R5, R6 and C5 are
additional component values to be determined. VOUT is mea-
sured with respect to SIGNAL REFERENCE.
10. Compute a maximum value of R5 and R6 based upon the
relationship
R5 + R6 ≤ VPS/100 µA
11. The voltage drop across R5 must be greater than
2 + 10 kΩ
1.2V
R4 + 2 kΩ
+
250 µA
+
VOUT
4 × R2
Volts
Therefore
R5
≥
2 + 10
kΩ
1. 2V
R4 + 2 kΩ
100
+ 250
µA
µA
+
VOUT
4 × R2 Ohms
Based upon the constraints of R5 + R6 (Step 10) and R5 (Step
11), select an interim value of R6.
12. Load current through RL returns to the junction of R5 and
R6, and flows back to VPS. Under maximum load condi-
tions, make sure the voltage drop across R5 is met as de-
fined in Step 11.
As a final check on the power supply voltages, verify that
the peak values of VA and VB are at least 2.5 volts less than
the voltage between +VS and –VS.
13. C5 is a bypass capacitor in the range of 0.1 µF to 1 µF.
Gain Phase Characteristics
To use an LVDT in a closed-loop mechanical servo application,
it is necessary to know the dynamic characteristics of the trans-
ducer and interface elements. The transducer itself is very quick
to respond once the core is moved. The dynamics arise prima-
rily from the interface electronics. Figures 14, 15 and 16 show
the frequency response of the AD698 LVDT Signal Conditioner.
Note that Figures 15 and 16 are basically the same; the differ-
ence is frequency range covered. Figure 15 shows a wider range
of mechanical input frequencies at the expense of accuracy.
10
0
–10
2.0µF
–20
0.1µF
–30
–40
0.33µF
–50
–60
–70
R2 = 81kΩ
fEXC = 2.5kHz
0
0.1µF
–60
–120
–180
2.0µF
0.33µF
–240
–300
–360
R2 = 81kΩ
fEXC = 2.5kHz
–420
0
100
1k
10k
FREQUENCY – Hz
Figure 14. Gain and Phase Characteristics vs. Frequency
(0 kHz–10 kHz)
–8–
REV. B
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