LF3330 查看數據表（PDF） - LOGIC Devices

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LF3330

Vertical Digital Image Filter

LOGIC Devices 

DEVICES INCORPORATED

LF3330

Vertical Digital Image Filter

3 set to “0”. Any LF3330s cascaded

after the first LF3330 should have

Bit 0 of Configuration Register 3 set

to “1”. When not cascading, Bit 0 of

Configuration Register 3 should be

set to “0”.

It is important to note that the first

multiplier on all cascaded devices

should not be used. This is because

the first multiplier does not have a

line buffer in front of it. The coeffi-

cient value sent to the first multi-

plier on a cascaded device should be

“0”.

Rounding

The filter output may be rounded by

adding the contents of one of the

sixteen round registers to the filter

output (see Figure 4). Each round

register is 32 bits wide and user-

programmable. This allows the filter’s

output to be rounded to any precision

required. Since any 32-bit value may

be programmed into the round

registers, the device can support

complex rounding algorithms as well

as standard half-LSB rounding. RSL3-0

determines which of the sixteen round

registers are used in the rounding

operation. A value of 0 on RSL3-0

selects round register 0. A value of 1

selects round register 1 and so on.

RSL3-0 may be changed every clock

cycle if desired. This allows the

rounding algorithm to be changed

every clock cycle. This is useful when

filtering interleaved data. If rounding

is not desired, a round register should

be loaded with 0 and selected as the

register used for rounding. Round

register loading is discussed in the

LF InterfaceTM section.

Output Select

The word width of the filter output

is 32 bits. However, only 16 bits

may be sent to DOUT15-0. The select

circuitry determines which 16 bits

are passed (see Table 1). There are

sixteen select registers which control

the select circuitry. Each select

register is 5 bits wide and user-

programmable. RSL3-0 determines

which of the sixteen select registers

are used in the select circuitry.

Select register 0 is chosen by loading

a 0 on RSL3-0. Select register 1 is

chosen by loading a 1 on RSL3-0 and

so on. RSL3-0 may be changed every

clock cycle if desired. This allows

the 16-bit window to be changed

every clock cycle. This is useful

when filtering interleaved data.

Select register loading is discussed

in the LF InterfaceTM section.

FIGURE 6. COEFFICIENT BANK LOADING SEQUENCE

COEFFICIENT SET 1

COEFFICIENT SET 2

COEFFICIENT SET 3

CLK

LD

CF11-0

ADDR1 COEF0

W1

COEF7 ADDR2 COEF0

W1: Coefficient Set 1 written to coefficient banks during this clock cycle.

W2: Coefficient Set 2 written to coefficient banks during this clock cycle.

W3: Coefficient Set 3 written to coefficient banks during this clock cycle.

W2

COEF7 ADDR3 COEF0

W3

COEF7

FIGURE 7. CONFIGURATION/CONTROL REGISTER LOADING SEQUENCE

CONFIG REG SELECT REG

ROUND REGISTER

LIMIT REGISTER

CLK

LD

CF11-0

W1

W2

W3

W4

ADDR1 DATA1 ADDR2 DATA1 ADDR3 DATA1 DATA2 DATA3 DATA4 ADDR4 DATA1 DATA2 DATA3 DATA4

W1: Configuration Register loaded with new data on this rising clock edge.

W2: Select Register loaded with new data on this rising clock edge.

W3: Round Register loaded with new data on this rising clock edge.

W4: Limit Register loaded with new data on this rising clock edge.

Video Imaging Products

6

11/08/2001–LDS.3330-M

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