LF3330 查看數據表（PDF） - LOGIC Devices
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LF3330 Datasheet PDF : 15 Pages
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DEVICES INCORPORATED
LF3330
Vertical Digital Image Filter
significant bits (CF11-9) determine if
the LF InterfaceTM will load coefficient
banks or configuration/control
registers (see Table 6). The nine least
significant bits (CF8-0) are the address
for whatever is to be loaded (see
Tables 7 through 9). For example, to
load address 15 of the coefficient
banks, the first data value into the
LF InterfaceTM should be 00FH. To
load limit register 10, the first data
value should be E0AH. The first
address value should be loaded into
the interface on the same clock cycle
that latches the HIGH to LOW
transition of LD (see Figures 6 and 7).
The next value(s) loaded into the
interface are the data value(s) which
will be stored in the bank or register
defined by the address value. When
loading coefficient banks, the interface
will expect eight values to be loaded
into the device after the address value.
The eight values are coefficients 0
through 7. When loading configura-
tion or select registers, the interface
will expect one value after the address
value. When loading round or limit
registers, the interface will expect four
TABLE 6. CF11-9 DECODE
11 10 9 DESCRIPTION
0 0 0 Coefficient Banks
0 0 1 Configuration Registers
0 1 1 Select Registers
1 0 1 Round Registers
1 1 1 Limit Registers
values after the address value. Fig-
ures 6 and 7 show the data loading
sequences for the coefficient banks
and configuration/control registers.
PAUSE allows the user to effectively
slow the rate of data loading through
the LF InterfaceTM. When PAUSE is
HIGH, the LF InterfaceTM is held until
PAUSE is returned to a LOW. Figures
8 through 11 display the effects of
PAUSE while leading coefficient and
control data.
Table 10 shows an example of
loading data into the coefficient
banks. The following data values
are written into address 10 of
coefficient banks 0 through 7: 210H,
543H, C76H, 9E3H, 701H, 832H,
F20H, 143H. Table 11 shows an
example of loading data into a
TABLE 7. ROUND REGISTERS
REGISTER
ADDRESS (HEX)
0
A00
1
A01
14
A0E
15
A0F
TABLE 8. SELECT REGISTERS
REGISTER
ADDRESS (HEX)
0
600
1
601
14
60E
15
60F
TABLE 9. LIMIT REGISTERS
REGISTER
ADDRESS (HEX)
0
E00
1
E01
14
E0E
15
E0F
TABLE 11. CONFIGURATION REGISTER LOADING FORMAT
CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0
1st Word - Address 0
0
1
0
0
0
0
0
0
0
1
0
2nd Word - Data
0
0
0
0
0
0
0
0
0
0
1
1
TABLE 12. ROUND REGISTER LOADING FORMAT
CF11 CF10 CF9 CF8 CF7 CF6 CF5 CF4 CF3 CF2 CF1 CF0
1st Word - Address 1
0
1
0
0
0
0
0
1
1
0
0
2nd Word - Data
R
R
R
R
1
0
1
0
0
0
1
0*
3rd Word - Data
R
R
R
R
1
1
1
1
0
1
0
0
4th Word - Data
R
R
R
R
1
0
0
0
0
0
1
1
5th Word - Data
R
R
R
R
0**
1
1
1
0
1
1
0
R = Reserved. Must be set to “0”.
* This bit represents the LSB of the Round Register.
** This bit represents the MSB of the Round Register.
Video Imaging Products
9
11/08/2001–LDS.3330-M
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