QL12X16B 查看數據表（PDF） - QuickLogic Corporation

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QL12X16B

Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA

QuickLogic Corporation 

Military 5.0V pASIC 1 Family

High Drive Buffer

Symbol

Parameter

tIN

High Drive Input Delay

tINI

High Drive Input,

Inverting Delay

Clock Drivers

Wired Together

1

2

3

4

1

2

3

4

Propagation Delays (ns) [4]

Fanout

12 24 48 72 96

4.0 4.9

3.5 5.0

4.0 4.8 5.6

4.1 4.8

4.2 5.1

3.7 5.2

4.2 5.0 5.8

4.3 5.0

[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25°C.

Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as

specified in the Operating Range.

8-16

16

Preliminary

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