QL12X16B 查看數據表（PDF） - QuickLogic Corporation
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QL12X16B Datasheet PDF : 16 Pages
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Military 5.0V pASIC 1 Family
QL12x16B
QL12X16B
AC CHARACTERISTICS at VCC = 5V, TA = 25°C (K = 1.00)
Logic Cell
Symbol
Parameter
tPD
tSU
tH
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
tRW
Combinatorial Delay [5]
Setup Time [5]
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set Delay
Reset Delay
Set Width
Reset Width
Propagation Delays (ns)
Fanout
1
2
3
4
8
1.7 2.2 2.6 3.2 5.2
2.1 2.1 2.1 2.1 2.1
0.0 0.0 0.0 0.0 0.0
1.0 1.5 1.9 2.5 4.6
2.0 2.0 2.0 2.0 2.0
2.0 2.0 2.0 2.0 2.0
1.7 2.1 2.6 3.2 5.2
1.5 1.9 2.2 2.7 4.3
1.9 1.9 1.9 1.9 1.9
1.8 1.8 1.8 1.8 1.8
Input Cells
Symbol
Parameter
tIN
tINI
tIO
tGCK
tGCKHI
tGCKLO
High Drive Input Delay [6]
High Drive Input, Inverting Delay [6]
Input Delay (bidirectional pad)
Clock Buffer Delay [7]
Clock Buffer Min High [7]
Clock Buffer Min Low [7]
Propagation Delays (ns) [4]
1
2
3
4
6
8
2.4 2.5 2.6 2.7 3.0 3.3
2.5 2.6 2.7 2.8 3.1 3.4
1.4 1.9 2.2 2.8 3.7 4.6
2.7 2.8 2.8 2.9 2.9 3.0
2.0 2.0 2.0 2.0 2.0 2.0
2.0 2.0 2.0 2.0 2.0 2.0
Symbol
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
tPLZ
Output Cell
Parameter
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-state [8]
Output Delay Low to Tri-state [8]
Propagation Delays (ns) [4]
Output Load Capacitance (pF)
30
50
75
100
150
2.7
3.4
4.2
5.0
6.7
2.8
3.7
4.7
5.6
7.6
4.0
4.9
6.1
7.3
9.7
3.6
4.2
5.0
5.8
7.3
2.9
3.3
Notes:
[6] See High Drive Buffer Table for more information.
[7] Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half col-
umns used does not affect clock buffer delay.
[8] The following loads are used for tPXZ:
8-17
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