QL12X16B 查看數據表（PDF） - QuickLogic Corporation
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QL12X16B Datasheet PDF : 16 Pages
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Military 5.0V pASIC 1 Family
PRODUCT SUMMARY
Product Summary
The pASIC 1 Family is a very-high-speed CMOS
user-programmable ASIC devices. The 768 logic cell
field-programmable gate array (FPGA) features
22,000 usable PLD gates of high-performance gen-
eral-purpose logic in a 208-pin PQFP and CQFP
package.
Low-impedance, metal-to-metal, ViaLink intercon-
nect technology provides nonvolatile custom logic
capable of operating above 150 MHz. Logic cell
delays under 2 ns, combined with input delays of
under 1.5 ns and output delays under 3 ns, permit
high-density programmable devices to be used with
today’s fastest microprocessors and DSPs.
Designs can be entered using QuickLogic’s Quick-
Works Toolkit or most popular third-party CAE tools.
QuickWorks combines Verilog/VHDL design entry
and simulation tools with device-specific place &
route and programming software. Ample on-chip
routing channels allow fast, fully automatic place and
route of designs using up to 100% of the logic and I/
O cells, while maintaining fixed pin-outs.
Pinout Diagram 68-Pin CPGA
PINOUT DIAGRAM 68-PIN CPGA
PIN
FUNC
PIN
B10
IO
B2
A10
IO
B1
B9
IO
C2
A9
IO
C1
B8
IO
D2
A8
IO
D1
B7
I/(SCLK)
E2
A7
I/CLK/(SM)
E1
B6
VCC
F2
A6
I
F1
B5
I
G2
A5
IO
G1
B4
IO
H2
A4
IO
H1
B3
IO
J2
A3
IO
J1
A2
IO
K1
FUNC
IO
IO
IO
IO
IO
IO
IO
IO
GND
IO
IO
IO
IO
IO
IO
IO
IO
PIN
FUNC
K2
IO
L2
IO
K3
IO
L3
IO
K4
IO
L4
IO
K5
I/(SI)
L5
I/CLK
K6
VCC
L6
I
K7
I/(SO)
L7
IO
K8
IO
L8
IO
K9
IO
L9
IO
L10
IO
PIN
K10
K11
J10
J11
H10
H11
G10
G11
F10
F11
E10
E11
D10
D11
C10
C11
B11
TABLE 2: CPGA 68 Function/Connector Pin Table
FUNC
IO
IO
IO
IO
IO
IO
IO
IO
GND
IO
IO
IO
IO
IO
IO
IO
IO
8-8
8
Preliminary
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