QL12X16B 查看數據表（PDF） - QuickLogic Corporation

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QL12X16B

Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA

QuickLogic Corporation 

Military 5.0V pASIC 1 Family

ABSOLUTE MAXIMUM RATINGS

Supply Voltage ........................-0.5 to 7.0V

Input Voltage................ -0.5 to VCC +0.5V

ESD Pad Protection.................... ±2000V

DC Input Current .......................±20 mA

Latch-up Immunity .................. ±200 mA

Storage Temperature .......-65°C to +150°C

Lead Temperature ...........................300°C

Symbol

5 Volt OPERATING RANGE

Parameter

VCC

TA

TC

K

Supply Voltage

Ambient Temperature

Case Temperature

Delay Factor

-0 Speed Grade

-1 Speed Grade

Military

Unit

Min Max

4.5

5.5 V

-55

°C

125 °C

0.39 1.82

0.39 1.56

Symbol

VIH

VIL

VOH

VOL

II

IOZ

CI

IOS

ICC

DC CHARACTERISTICS over 5V operating range

Parameter

Input HIGH Voltage

Input LOW Voltage

Output HIGH Voltage

Output LOW Voltage

Input Leakage Current

3-State Output Leakage Current

Input Capacitance [1]

Output Short Circuit Current [2]

D.C. Supply Current [3]

Conditions

IOH = -4 mA

IOH = 16 mA

IOH = -10 µA

IOL = 8 mA

IOL = 10 µA

VI = VCC or GND

VI = VCC or GND

VO = GND

VO = VCC

VI, VIO = VCC or GND

Min Max Unit

2.0

V

0.8 V

3.7

V

2.4

V

VCC-0.1

V

0.4 V

0.1 V

-10

10 µA

-10

10 µA

10 pF

-10

-90 mA

40

160 mA

20 mA

Notes:

[1] Capacitance is sample tested only. CI = 20 pF max on I/(SI).

[2] Only one output at a time. Duration should not exceed 30 seconds.

[3] Maximum Icc for military grade is 20 mA. For AC conditions use the formula described in the databook,

Section 9 - Power vs Operating Frequency.

[4] Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25°C. Mul-

tiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the

Operating Range.

[5] These limits are derived from a representative selection of the slowest paths through the pASIC logic cell

including net delays. Worst case delay values for specific paths should be determined from timing analysis

of your particular design.

8-14

14

Preliminary

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