T4312816A 查看數據表（PDF） - Taiwan Memory Technology

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T4312816A

8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM

Taiwan Memory Technology 

tm TE

CH

Burst Length and Sequence

(Burst of Two)

Starting Address

(column address A0 binary)

0

1

Preliminary T4312816A

Sequential Addressing

Sequence (decimal)

0,1

1,0

Interleave Addressing

Sequence (Decimal)

0,1

1,0

(Burst of Four)

Starting Address

(column address A1-A0 binary)

00

01

10

11

Sequential Addressing

Sequence (decimal)

0,1,2,3

1,2,3,0

2,3,0,1

3,0,1,2

Interleave Addressing

Sequence (Decimal)

0,1,2,3

1,0,3,2

2,3,0,1

3,2,1,0

(Burst of Eight)

Starting Address

(column address A2-A0 binary)

000

001

010

011

Sequential Addressing

Sequence (decimal)

0,1,2,3,4,5,6,7

1,2,3,4,5,6,7,0

2,3,4,5,6,7,0,1

3,4,5,6,7,0,1,2

Interleave Addressing

Sequence (Decimal)

0,1,2,3,4,5,6,7

1,0,3,2,5,4,7,6

2,3,0,1,6,7,4,5

3,2,1,0,7,6,5,4

100

4,5,6,7,0,1,2,3

4,5,6,7,0,1,2,3

101

5,6,7,0,1,2,3,4

5,4,7,6,1,0,3,2

110

6,7,0,1,2,3,4,5

6,7,4,5,2,3,0,1

111

7,0,1,2,3,4,5,6

7,6,5,4,3,2,1,0

Full page burst is an extension of the above tables of Sequential Addressing, with the length being 512 for

8Mx16 divice.

POWER UP SEQUENCE

1. Apply power and start clock, attempt to maintain CKE = ‘H’ , L(U)DQM = ‘H’ and the other pin are NOP

condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue mode register set command to initalize the mode register.

Cf.) Sequence of 4 & 5 is regardless of the order.

TM Technology Inc. reserves the right

P.11

to change products or specifications without notice.

Publication Date:APR. 2003

Revision: 0.B

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