CXB1455R 查看數據表（PDF） - Sony Semiconductor

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CXB1455R

VGA/SVGA/XGA 24-bit Transmitter

Sony Semiconductor 

CXB1455R

CE Pin Control

The CE pin should be controlled as follows.

When the power is turned ON or SFTCLK stops, or when the SFTCLK input signal falls into the disorder while

the SFTCLK frequency is varied, the CE pin should be set to Low level and the CE pin should be set to High

level after the SFTCLK frequency stabilizes. (Figs. 9 and 10)

When the power supply and SFTCLK stabilize

VCC

SFTCLK

CE

200µs or more

Fig. 9. CE timing when power supply is turned ON

When SFTCLK does not stabilize

When SFTCLK stabilizes

SFTCLK

CE

∗

200µs or more

∗ When SFTCLK stops or the frequencies of 15MHz or less and 75MHz or more are input.

Fig. 10. CE timing when SFTCLK input signal is not stabilized

–8–

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