SDA5650 查看數據表（PDF） - Infineon Technologies

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SDA5650

VPS / PDC-plus Decoder

Infineon Technologies 

SDA 5650/X

Control Register:

Bit Number: 7

6

5

4

3

2

1

0

T4

T3

T2

T1

MAB HDT PDC/ FOR1/

VPS FOR2

Default: All bits are set to 0 on power-up.

Bits 4 through 7 are used for test purposes and must not be changed for normal

operation by user software!

Bit 0:

determines, which kind of data is accessed via the I2C Bus when PDC

mode is active:

0

BDSP 8/ 30/ 2 data accessible

Value

1

BDSP 8/ 30/ 1 or header row

data accessible (refer to description of

Bit 2)

Bit 1:

determines the operating mode:

0

VPS mode active

Value

1

PDC mode active

Bit 2:

determines whether BDSP 8/30/1-data or header row data is

accessible:

0

BDSP 8/30/1 data accessible

Value

1

Bytes of teletext header in mode A or B

(see Bit 3)

Bit 3:

determines mode of teletext header access:

0

Mode A: header bytes in order 38-45,

30-37

Value

1

Mode B: header bytes in order 22-29,

14-21

Semiconductor Group

11

02.97

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