SDA5650 查看數據表（PDF） - Infineon Technologies

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SDA5650

VPS / PDC-plus Decoder

Infineon Technologies 

SDA 5650/X

In VPS mode, the extracted data bits of TV line no. 16 are checked for biphase errors.

With no biphase errors encountered, the acquired bytes are stored in the transfer

register to the I2C Bus. That transfer is signalled by a H/L transition of the DAVN output,

as well.

In TTX header mode A bytes 38-45 and 30-37 are accessed in this order. This assures

software compatibility to the SDA 5649. In mode B bytes 22-29 and 14-21 are accessed

in this order.

In all three operating modes data are updated when a new data line has been received,

provided that the chip is not accessed via the I2C Bus at the same time.

A micro controller can read the stored bytes via the I2C-Bus interface at any time.

However, one must be aware that the storage of new data from the acquisition interface

is inhibited as long as the PDC decoder is being accessed via the I2C Bus.

Note: In order to achieve maximum system performance it is recommended to start the

SDA 5650 in VPS mode (state after power on) and read the register to check

whether line 16 is received. After reception of VPS data inline 16 the SDA 5650

can be switched to 8/30 mode and waiting for packet 8/30 data. Since VPS data

in line 16 is transmitted every frame and PDC data in packet 8/30 is transmitted

nearly every second the recognition of both VPS and 8/30 packets can be done

within PDC-system constraints (about 1 sec).

2.2 I2C Bus

2.2.1 General Information

The I2C-Bus interface implemented on the PDC decoder is a slave transmitter/receiver,

i. e., both reading from and writing to the PDC / VPS decoder is possible. The clock line

SCL is controlled only by the bus master usually being a micro controller, whereas the

SDA line is controlled either by the master or by the slave. A data transfer can only be

initiated by the bus master when the bus is free, i. e., both SDA and SCL lines are in a

high state. As a general rule for the I2C Bus, the SDA line changes state only when the

SCL line is low. The only exception to that rule are the Start Condition and the Stop

Condition. Further Details are given below. The following abbreviations are used:

START:

AS:

AM:

NAM:

STOP:

Start Condition generated by master

Acknowledge by slave

Acknowledge by master

No Acknowledge by master

Stop condition generated by master

Semiconductor Group

9

02.97

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