MX812J 查看數據表（PDF） - MX-COM Inc
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MX812J Datasheet PDF : 13 Pages
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VSR CODEC with DRAM CONTROL
Application Information ......
+ 5.0V
5
MX812 PRELIMINARY INFORMATION
+ 5.0V
VDD WE
CAS
RAS1
A10/R2
A9
A8
A7
MX812 A6
A5
A4
A3
A2
A1
A0
DGND
D
VCC
W
CAS
RAS
A10
A9
A8
A7 4Mbit.
A6 DRAM
A5
A4
A3
A2
A1
A0
Q
D
VSS
VDD WE
CAS
RAS1
A10/R2
A9
A8
A7
MX812 A6
A5
A4
A3
A2
A1
A0
DGND
D
VCC
W
CAS
RAS
A9
A8
A7 1Mbit.
A6 DRAM.
A5 No.1
A4
A3
A2
A1
A0
Q
D
VSS
VCC
W
CAS
RAS
A9
A8
A7 1Mbit.
A6 DRAM.
A5 No.2
A4
A3
A2
A1
A0
Q
D
VSS
Figure 4 - Example DRAM Connections
Choice of DRAM Devices
DRAM devices chosen should be standard 1,048,576 x 1 or 4,194,304 x 1 Dynamic Random Access
memories, with ‘CAS before RAS’ refresh, and a Row Address access time of 200 nano-seconds or less.
BANK A
SELECT
INPUTS
B
'HC04
'HC00
WE
CAS
RAS1
A10/R2
A9
A8
A7
MX812 A6
A5
A4
A3
A2
A1
A0
D
W
CAS
RAS
A10
A9
A8
A7
A6 4Mbit
A5 DRAM
A4 No. 1
A3
A2
A1
A0
Q
D
W
CAS
RAS
A10
A9
A8
A7
A6 4Mbit
A5 DRAM
A4 No. 2
A3
A2
A1
A0
Q
D
Figure 5 - Use of External Elements to Drive Two 4-MBit DRAM Chips
Driving Two 4-MBit DRAM Sections
By adding external logic circuitry, the MX812 can be configured
to drive two 4-MBit DRAM sections. This will have the effect of
doubling the available storage time. i.e. 4 minutes at 32kbps.
With reference to the circuitry shown in Figure 5:
With the Mode Register MS Bit set to “0” the MX812 treats the
DRAM sections as two 1-Mbit devices. The external logic makes
each 4-MBit DRAM appear as four 1-MBit banks selected by the
Bank Select lines ‘A’ and ‘B.’
Bank Select
Inputs
A
B
0
0
1
0
0
1
1
1
DRAM No 1
Pages
0 – 1023
DRAM No 2
Pages
1024 – 2047
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054
Doc. # 20480076.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
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