STLC3065 查看數據表（PDF） - STMicroelectronics

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STLC3065

WLL SUBSCRIBER LINE INTERFACE CIRCUIT

STMicroelectronics 

STLC3065

Depending on the P1,P2 control bits the ring

waveform can be applied to both 2W ports

(TIP1/RING1 and TIP2/RING2) or to one of the

two (see also table2).

The ring trip detection is performed sensing the

variation of the AC line impedance from on hook

(relatively high) to off-hook (low). This particular

ring trip method allows to operate without DC off-

set superimposed on the ring signal and therefore

obtaining the maximum possible ring level on the

load starting from a given negative battery.

It should be noted that such a method is opti-

mised for operation on short loop applications and

may not operate properly in presence of long loop

applications (>500Ω).

Once ring trip is detected, the DET output is acti-

vated (logic level low), at this point the card con-

troller or a simple logic circuit should stop the D2

toggling in order to effectively disconnect the ring

signal and then set the STLC3065 in the proper

operating mode (Normally ACTIVE).

RING LEVEL IN PRESENCE OF MORE TELE-

PHONE IN PARALLEL.

As already mentioned above the maximum cur-

rent that can be drawn from the Vpos supply is

controlled and limited via the external RSENSE.

This will limit also the power available at the self

generated negative battery.

If for any reason the ringer load will be too high

the self generated battery will drop in order to

keep the power consumption to the fixed limit and

therefore also the ring voltage level will be re-

duced.

In the typical application with RSENSE = 110mW

the peak current from Vpos is limited to about

900mA, which correspond to an average current

of 700mA max. In this condition the STLC3065

can drive up to 3REN with a ring frequency

fr=25Hz (1REN = 1800Ω + 1.0µF, European

standard).

In order to drive up to 5REN (1REN= 6930Ω +

8mF, US standard) it is necessary to modify the

external components as follows:

CREV = 15nF

RD = 2.2 KΩ

Power On Requirements

In order to avoid damage to the device when

Vpos is first applied it is recommended to keep all

the logic inputs to a low logic level (0V) until Vpos

is > 5.5V.

In case this power up sequence cannot be guar-

anteed, it’s recommended to connect a shottky di-

ode (BAT46 or equivalent) between VBAT and

BGND (see figure 7).

Figure 7. Shottky diode connection

BGND

STLC3065

VBAT

BAT46

Layout Recommendation

A properly designed PCB layout is a basic issue

to guarantee a correct behaviour and good noise

performances.

Particular care must be taken on the ground con-

nection and in this case the star configuration al-

lows surely to avoid possible problems (see Appli-

cation Diagram Fig. 8).

The ground of the power supply (VPOS) has to

be connected to the center of the star, let’s call

this point PGND. This point should show a resis-

tance as low as possible, that means it should be

a ground plane.

Noise sources can be identified in not enough

good grounds, not enough low impedance sup-

plies and parasitic coupling between PCB tracks

and high impedance pins of the device.

In particular, to avoid noise problems, layout

should prevent any coupling between the DC/DC

converter components and analog pins that are

referred to AGND (ex: RD, IREF, RTH, RLIM,

VF). As a first reccomendation the components

CV, L, D1, CVPOS, RSENSE should be kept as

close as possible to each other and isolated from

the other components.

Additional improvements can be obtained:

decoupling the center of the star from the analog

ground of STLC3065 using small chokes.

adding a capacitor in the range of 100nF between

VPOS and AGND in order to filter the switch fre-

quency on VPOS.

11/27

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