STLC3065 查看數據表（PDF） - STMicroelectronics

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产品描述 (功能)

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STLC3065

WLL SUBSCRIBER LINE INTERFACE CIRCUIT

STMicroelectronics 

STLC3065

PIN DESCRIPTION (continued)

N.

35

23

21

22

24

1

2

3

4

5

8

6

7

33

12

13

10

11

9

44

38,39,

40

Name

VBAT

GATE

VF

CLK

RSENSE

D0

D1

D2

P1

P2

DET

DET1

DET2

CSVR

RTTX

FTTX

CTTX1

CTTX2

CKTTX

VBAT1

NC

Fu nction

Regulated battery voltage self generated by the device via DC/DC converter. Must be shorted

to VBAT1.

Driver for external Power MOS transistor.

Feedback input for DC/DC converter controller.

Power Switch Controller Clock (typ. 125KHz). From version marked STLC3065 A5, this pin

can also be connected to CVCC or AGND. When the CLK pin is connected to CVCC an

internal auto-oscillation is internally generated and it is used instead of the external clock.

When the CLK pin is connected to AGND, the GATE output is disabled.

Voltage input for current sensing. RSENSE should be connected close to this pin and VPOS

pin. The PCB layout should minimize the extra resistance introduced by the copper tracks.

Control Interface: input bit 0.

Control Interface: input bit 1.

Control interface: input bit 2.

Control Interface: port 1 selection bit

Control Interface: port 2 selection bit

Logic interface output of the supervision detector (active low).

Logic interface output of thr linr port 1 detector (active low)

Logic interface output of thr linr port 2 detector (active low)

Battery supply filter capacitor.

Metering pulse cancellation buffer output. TTX filter network should be connected to this point.

If not used should be left open.

Metering pulse buffer input this signal is sent to the line and used to perform TTX filtering.

Metering burst shaping external capacitor.

Metering burst shaping external capacitor.

Metering pulse clock input (12 KHz or 16KHz square wave).

Frame connection. Must be shorted to VBAT.

Not connected.

FUNCTIONAL DESCRIPTION

The STLC3065 is a device specifically developed

for WLL application.

It is based on a SLIC core, on purpose optimised

for this application, with the addition of a DC/DC

converter controller and a dual port in order to ful-

fil the WLL requirements.

The SLIC core performs the standard feeding,

signalling and transmission functions.

It can be set in three different operating modes

via the D0, D1, D2 pins of the control logic inter-

face (0 to 3.3V logic levels). The loop status is

carried out on the DET pin (active low).The DET

pin is an open drain output to allow easy interfac-

ing with both 3.3V and 5V logic levels.

The three possible SLIC core operating modes

are:

Power Down (PWD)

4/27

Active

Ringing

Table 1 shows how to set the different SLIC core

operating modes.

Table 1. SLIC core operating modes.

D0 D1 D2

Operating Mode

0

0

X Power Down

0

1

0 Active Normal Polarity

0

1

1 Active Reverse Polarity

1

1

0 Active TTX injection (N.P.)

1

1

1 Active TTX injection (R.P.)

1

0

0/1 Ring (D2 bit toggles @ fring)

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